MEM_CTRL_CLR_IDX = 1 << 1, /* "clr_idx" bit */
};
+/* LWLA1034 long register addresses.
+ */
+enum {
+ LREG_CAP_CTRL = 10, /* capture control bits */
+ LREG_TEST_ID = 100, /* constant test ID */
+};
+
+/** Flag bits for LREG_CAP_CTRL.
+ */
+enum {
+ CAP_CTRL_TRG_EN = 1 << 0, /* "trg_en" bit */
+ CAP_CTRL_CLR_TIMEBASE = 1 << 2, /* "do_clr_timebase" bit */
+ CAP_CTRL_FLUSH_FIFO = 1 << 4, /* "flush_fifo" bit */
+ CAP_CTRL_CLR_FIFOFULL = 1 << 5, /* "clr_fifo32_ful" bit */
+ CAP_CTRL_CLR_COUNTER = 1 << 6, /* "clr_cntr0" bit */
+};
+
/** Register/value pair.
*/
struct regval_pair {
regvals = devc->reg_write_seq;
regvals[0].reg = REG_LONG_ADDR;
- regvals[0].val = 10;
+ regvals[0].val = LREG_CAP_CTRL;
regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 0;
if (ret != SR_OK)
return ret;
- ret = lwla_read_long_reg(sdi->conn, 100, &value);
+ ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
if (ret != SR_OK)
return ret;
/* Ignore the value returned by the first read */
- ret = lwla_read_long_reg(sdi->conn, 100, &value);
+ ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
if (ret != SR_OK)
return ret;
regvals[1].val = MEM_CTRL_WRITE;
regvals[2].reg = REG_LONG_ADDR;
- regvals[2].val = 10;
+ regvals[2].val = LREG_CAP_CTRL;
regvals[3].reg = REG_LONG_LOW;
- regvals[3].val = 0x74;
-
+ regvals[3].val = CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO
+ | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER;
regvals[4].reg = REG_LONG_HIGH;
regvals[4].val = 0;
regvals = devc->reg_write_seq;
regvals[0].reg = REG_LONG_ADDR;
- regvals[0].val = 10;
+ regvals[0].val = LREG_CAP_CTRL;
regvals[1].reg = REG_LONG_LOW;
- regvals[1].val = 1;
+ regvals[1].val = CAP_CTRL_TRG_EN;
regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;