uint8_t triggerselect;
struct triggerinout triggerinout_conf;
struct triggerlut lut;
+ uint8_t regval;
if (sdi->status != SR_ST_ACTIVE)
return SR_ERR_DEV_CLOSED;
/* Start acqusition. */
gettimeofday(&devc->start_tv, 0);
- sigma_set_register(WRITE_MODE, 0x0d, devc);
+ regval = WMR_TRGRES | WMR_SDRAMWRITEEN;
+#if ASIX_SIGMA_WITH_TRIGGER
+ regval |= WMR_TRGEN;
+#endif
+ sigma_set_register(WRITE_MODE, regval, devc);
std_session_send_df_header(sdi);
static int sigma_fpga_init_la(struct dev_context *devc)
{
/* Initialize the logic analyzer mode. */
+ uint8_t mode_regval = WMR_SDRAMINIT;
uint8_t logic_mode_start[] = {
REG_ADDR_LOW | (READ_ID & 0xf),
REG_ADDR_HIGH | (READ_ID >> 4),
REG_READ_ADDR, /* Read scratch register. */
REG_ADDR_LOW | (WRITE_MODE & 0xf),
- REG_DATA_LOW | 0x0,
- REG_DATA_HIGH_WRITE | 0x8,
+ REG_DATA_LOW | (mode_regval & 0xf),
+ REG_DATA_HIGH_WRITE | (mode_regval >> 4),
};
uint8_t result[3];
sr_info("Downloading sample data.");
- /* Stop acquisition. */
- sigma_set_register(WRITE_MODE, 0x11, devc);
+ /*
+ * Ask the hardware to stop data acquisition. Reception of the
+ * FORCESTOP request makes the hardware "disable RLE" (store
+ * clusters to DRAM regardless of whether pin state changes) and
+ * raise the POSTTRIGGERED flag.
+ */
+ sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
+ do {
+ modestatus = sigma_get_register(READ_MODE, devc);
+ } while (!(modestatus & RMR_POSTTRIGGERED));
/* Set SDRAM Read Enable. */
- sigma_set_register(WRITE_MODE, 0x02, devc);
+ sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
/* Get the current position. */
sigma_read_pos(&stoppos, &triggerpos, devc);
/* Check if trigger has fired. */
modestatus = sigma_get_register(READ_MODE, devc);
- if (modestatus & 0x20) {
+ if (modestatus & RMR_TRIGGERED) {
trg_line = triggerpos >> 9;
trg_event = triggerpos & 0x1ff;
}
#define CHUNK_SIZE 1024
+/* WRITE_MODE register fields. */
+#define WMR_SDRAMWRITEEN (1 << 0)
+#define WMR_SDRAMREADEN (1 << 1)
+#define WMR_TRGRES (1 << 2)
+#define WMR_TRGEN (1 << 3)
+#define WMR_FORCESTOP (1 << 4)
+#define WMR_TRGSW (1 << 5)
+/* not used: bit position 6 */
+#define WMR_SDRAMINIT (1 << 7)
+
+/* READ_MODE register fields. */
+#define RMR_SDRAMWRITEEN (1 << 0)
+#define RMR_SDRAMREADEN (1 << 1)
+/* not used: bit position 2 */
+#define RMR_TRGEN (1 << 3)
+#define RMR_ROUND (1 << 4)
+#define RMR_TRIGGERED (1 << 5)
+#define RMR_POSTTRIGGERED (1 << 6)
+/* not used: bit position 7 */
+
/*
* The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024];
*/