if (write_longcommand(devc, cmd, arg) != SR_OK)
return SR_ERR;
+ cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
+ arg[0] = devc->trigger_edge[stage] & 0xff;
+ arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
+ arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
+ arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
+ if (write_longcommand(devc, cmd, arg) != SR_OK)
+ return SR_ERR;
+
return SR_OK;
}
arg[1] = ((readcount - 1) & 0xff00) >> 8;
arg[2] = ((readcount - 1) & 0xff0000) >> 16;
arg[3] = ((readcount - 1) & 0xff000000) >> 24;
- if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
+ if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
return SR_ERR;
arg[0] = ((delaycount - 1) & 0xff);
arg[1] = ((delaycount - 1) & 0xff00) >> 8;
arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
- if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
+ if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
return SR_ERR;
/* Flag register. */
sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
devc->trigger_mask[i] = 0;
devc->trigger_value[i] = 0;
+ devc->trigger_edge[i] = 0;
}
devc->num_stages = 0;
stage = 0;
for (tc = ch->trigger; tc && *tc; tc++) {
devc->trigger_mask[stage] |= channel_bit;
- if (*tc == '1')
+ if ((*tc == '1') || (*tc == 'r'))
devc->trigger_value[stage] |= channel_bit;
+ if ((*tc == 'r') || (*tc == 'f'))
+ devc->trigger_edge[stage] |= channel_bit;
stage++;
/* Only supporting parallel mode, with up to 4 stages. */
if (stage > 3)
#define NUM_CHANNELS 32
#define NUM_TRIGGER_STAGES 4
-#define TRIGGER_TYPE "01"
+#define TRIGGER_TYPE "01rf"
#define CLOCK_RATE SR_MHZ(100)
#define MIN_NUM_SAMPLES 4
#define DEFAULT_SAMPLERATE SR_MHZ(100)
#define CMD_SET_TRIGGER_MASK 0xc0
#define CMD_SET_TRIGGER_VALUE 0xc1
#define CMD_SET_TRIGGER_CONFIG 0xc2
+#define CMD_SET_TRIGGER_EDGE 0xc3
/* Trigger config */
#define TRIGGER_START (1 << 3)
uint32_t channel_mask;
uint32_t trigger_mask[4];
uint32_t trigger_value[4];
+ uint32_t trigger_edge[4];
int num_stages;
uint16_t flag_reg;