srd: uart: Add missing initialization.

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index f0f40c92289bc2c59f7d5a1dd68050ba19e2744a..5098977cc074e3d841cc39c9edcd9224a146ce02 100644 (file)
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -220,6 +220,7 @@ class Decoder(srd.Decoder):
         self.startbit = [-1, -1]
         self.cur_data_bit = [0, 0]
         self.databyte = [0, 0]
+        self.paritybit = [-1, -1]
         self.stopbit1 = [-1, -1]
         self.startsample = [-1, -1]