static const uint32_t devopts_cg_digital[] = {
SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_LOGIC_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
static const char *coupling[] = {
SR_TRIGGER_ONE,
};
+static const char *logic_thresholds[] = {
+ "1.2V Logic",
+ "1.5V Logic",
+ "1.8V Logic",
+ "2.5V Logic",
+ "3.0V Logic",
+ "3.3V/5.0V Logic",
+};
+
+/* Values taken from USB wireshark capture */
+static const uint16_t logic_threshold_values[] = {
+ 0x600,
+ 0x770,
+ 0x8ff,
+ 0xc70,
+ 0xeff,
+ 0xfff,
+};
+
static void mso_update_trigger_slope(struct dev_context *devc)
{
switch (devc->trigger_source) {
devc->ctltrig_pos |= sign_bit;
}
+static void mso_update_logic_threshold_value(struct dev_context *devc)
+{
+ devc->logic_threshold_value = logic_threshold_values[devc->logic_threshold];
+}
+
static GSList* scan_handle_port(GSList *devices, struct sp_port *port)
{
int usb_vid, usb_pid;
devc->cur_rate = SR_KHZ(10);
devc->dso_probe_factor = 10;
devc->limit_samples = MSO_NUM_SAMPLES;
+ devc->logic_threshold = ARRAY_SIZE(logic_thresholds) - 1; // 3.3V/5V
+ mso_update_logic_threshold_value(devc);
devc->protocol_trigger.spimode = 0;
for (i = 0; i < ARRAY_SIZE(devc->protocol_trigger.word); i++) {
case SR_CONF_HORIZ_TRIGGERPOS:
*data = g_variant_new_double(devc->horiz_triggerpos);
break;
+ case SR_CONF_LOGIC_THRESHOLD:
+ if (!cg_is_digital(cg))
+ return SR_ERR_ARG;
+ *data = g_variant_new_string(logic_thresholds[devc->logic_threshold]);
+ break;
default:
return SR_ERR_NA;
}
devc->dso_probe_factor = tmp_u64;
mso_limit_trigger_level(devc);
break;
+ case SR_CONF_LOGIC_THRESHOLD:
+ if (!cg_is_digital(cg))
+ return SR_ERR_ARG;
+ idx = std_str_idx(data, ARRAY_AND_SIZE(logic_thresholds));
+ if (idx < 0)
+ return SR_ERR_ARG;
+ devc->logic_threshold = idx;
+ mso_update_logic_threshold_value(devc);
+ break;
default:
return SR_ERR_NA;
}
case SR_CONF_TRIGGER_MATCH:
*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
break;
+ case SR_CONF_LOGIC_THRESHOLD:
+ if (!cg_is_digital(cg))
+ return SR_ERR_ARG;
+ *data = g_variant_new_strv(ARRAY_AND_SIZE(logic_thresholds));
+ break;
default:
return SR_ERR_NA;
}
return ret;
/* set dac offset */
- ret = mso_dac_out(sdi, devc->dac_offset);
+ ret = mso_dac_out(sdi, DAC_SELECT_DSO | devc->dac_offset);
if (ret != SR_OK)
return ret;
{
struct dev_context *devc = sdi->priv;
- return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
+ return mso_dac_out(sdi, DAC_SELECT_LA | devc->logic_threshold_value);
}
SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
struct dev_context *devc = sdi->priv;
uint16_t ops[] = {
- mso_trans(REG_DAC1, (val >> 8) & 0xff),
- mso_trans(REG_DAC2, val & 0xff),
+ mso_trans(REG_DAC_MSB, (val >> 8) & 0xff),
+ mso_trans(REG_DAC_LSB, val & 0xff),
mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_LOAD_DAC),
};
uint16_t ctltrig_pos;
uint8_t status;
- uint8_t la_threshold;
+ uint8_t logic_threshold;
+ uint16_t logic_threshold_value;
uint64_t cur_rate;
const char *coupling;
uint16_t dso_probe_factor;
#define REG_CLKRATE1 9
#define REG_CLKRATE2 10
#define REG_TRIG_WIDTH 11
-#define REG_DAC1 12
-#define REG_DAC2 13
+#define REG_DAC_MSB 12
+#define REG_DAC_LSB 13
/* possibly bank agnostic: */
#define REG_CTL1 14
TRIG_POS_IS_NEGATIVE = 1 << 15,
};
+/* bits - REG_DAC */
+enum {
+ DAC_SELECT_DSO = 0 << 15,
+ DAC_SELECT_LA = 1 << 15,
+};
+
/* bits - REG_CTL1 */
#define BIT_CTL1_RESETFSM (1 << 0)
#define BIT_CTL1_ARM (1 << 1)
{ SR_HZ(100), 0x9f0f, 0x20 },
};
-/* FIXME: Determine corresponding voltages */
-static const uint16_t la_threshold_map[] = {
- 0x8600, 0x8770, 0x88ff, 0x8c70, 0x8eff, 0x8fff,
-};
-
#endif