self.state = 'WAIT FOR RISING EDGE'
else:
- raise Exception('Invalid state: %d' % self.state)
+ raise Exception('Invalid state: %s' % self.state)
self.oldval = val
if self.is_data_bit(scl, sda):
self.get_ack(scl, sda)
else:
- raise Exception('Invalid state %d' % self.STATE)
+ raise Exception('Invalid state: %s' % self.state)
# Save current SDA/SCL values for the next round.
self.oldscl = scl
self.state = 'IGNORE START REPEAT'
self.data = []
else:
- raise Exception('Invalid state: %d' % self.state)
+ raise Exception('Invalid state: %s' % self.state)
else:
pass # TODO?
else:
- raise Exception('Invalid state: %d' % self.state)
+ raise Exception('Invalid state: %s' % self.state)
else:
pass # TODO?
else:
- raise Exception('Invalid state: %d' % self.state)
+ raise Exception('Invalid state: %s' % self.state)
elif self.state[rxtx] == 'GET STOP BITS':
self.get_stop_bits(rxtx, signal)
else:
- raise Exception('Invalid state: %d' % self.state[rxtx])
+ raise Exception('Invalid state: %s' % self.state[rxtx])
# Save current RX/TX values for the next round.
self.oldbit[rxtx] = signal