zeroplus-logic-cube: Add external clock settings

Enables the "external clock mode" in the Zeroplus LAP-C Logic
Cube driver (falling and rising edge) so that this mode also can be used in
sigrok-cli and pulseview

diff --git a/src/hardware/zeroplus-logic-cube/analyzer.c b/src/hardware/zeroplus-logic-cube/analyzer.c
index 0617d227467e840548a93c823678c89c0c199ca1..0a32e5e3ebf79ce0366321cda914e161ff28f5b4 100644 (file)
--- a/src/hardware/zeroplus-logic-cube/analyzer.c
+++ b/src/hardware/zeroplus-logic-cube/analyzer.c
@@ -114,6 +114,9 @@ static int g_trigger_count = 1;
 static int g_filter_status[8] = { 0 };
 static int g_filter_enable = 0;
 
+static int g_ext_clock = 0;
+static ext_clock_edge_t g_ext_clock_edge = LAPC_CLOCK_EDGE_RISING;
+
 static int g_freq_value = 1;
 static int g_freq_scale = FREQ_SCALE_MHZ;
 static int g_memory_size = MEMORY_SIZE_8K;
@@ -459,7 +462,14 @@ SR_PRIV void analyzer_configure(libusb_device_handle *devh)
        gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
 
        /* Sele_Inside_Outside_Clock */
-       gl_reg_write(devh, CLOCK_SOURCE, 0x03);
+       if (!g_ext_clock)
+               gl_reg_write(devh, CLOCK_SOURCE, 0x01);
+       else {
+               if (g_ext_clock_edge == LAPC_CLOCK_EDGE_RISING)
+                       gl_reg_write(devh, CLOCK_SOURCE, 0x02);
+               else
+                       gl_reg_write(devh, CLOCK_SOURCE, 0x0);
+       }
 
        /* Set_Trigger_Status */
        for (i = 0; i < 8; i++)
@@ -579,6 +589,12 @@ SR_PRIV void analyzer_set_trigger_count(int count)
        g_trigger_count = count;
 }
 
+SR_PRIV void analyzer_set_ext_clock(int enable, ext_clock_edge_t edge)
+{
+       g_ext_clock = enable;
+       g_ext_clock_edge = edge;
+}
+
 SR_PRIV void analyzer_set_freq(int freq, int scale)
 {
        g_freq_value = freq;

diff --git a/src/hardware/zeroplus-logic-cube/analyzer.h b/src/hardware/zeroplus-logic-cube/analyzer.h
index 29f2c29229f311e69f08ea447396eaafbfa844e2..4a68b57a6b31257c7c59a7f2f57798bded9ee51f 100644 (file)
--- a/src/hardware/zeroplus-logic-cube/analyzer.h
+++ b/src/hardware/zeroplus-logic-cube/analyzer.h
@@ -34,6 +34,7 @@
 
 #include <libusb.h>
 #include <libsigrok/libsigrok.h>
+#include "protocol.h"
 
 #define STATUS_FLAG_NONE       0x00
 #define STATUS_FLAG_RESET      0x01
@@ -74,6 +75,7 @@
 #define COMPRESSION_ENABLE     0x8001
 #define COMPRESSION_DOUBLE     0x8002
 
+SR_PRIV void analyzer_set_ext_clock(int enable, ext_clock_edge_t edge);
 SR_PRIV void analyzer_set_freq(int freq, int scale);
 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address);
 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address);

diff --git a/src/hardware/zeroplus-logic-cube/api.c b/src/hardware/zeroplus-logic-cube/api.c
index a7c5933d7f996f740c0c5cddc4137696385a19fa..fc4ffd677dbe2ed2986df331e73aa30481680b91 100644 (file)
--- a/src/hardware/zeroplus-logic-cube/api.c
+++ b/src/hardware/zeroplus-logic-cube/api.c
@@ -18,6 +18,7 @@
  */
 
 #include <config.h>
+#include "analyzer.h"
 #include "protocol.h"
 
 #define USB_INTERFACE                  0
@@ -67,6 +68,13 @@ static const uint32_t devopts[] = {
        SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
        SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
        SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+       SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
+       SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+};
+
+static const char *ext_clock_edges[] = {
+       [LAPC_CLOCK_EDGE_RISING] = "rising",
+       [LAPC_CLOCK_EDGE_FALLING] = "falling",
 };
 
 static const int32_t trigger_matches[] = {
@@ -359,6 +367,7 @@ static int config_get(uint32_t key, GVariant **data,
        const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 {
        struct dev_context *devc;
+       const char *ext_clock_text;
 
        (void)cg;
 
@@ -377,6 +386,13 @@ static int config_get(uint32_t key, GVariant **data,
        case SR_CONF_VOLTAGE_THRESHOLD:
                *data = std_gvar_tuple_double(devc->cur_threshold, devc->cur_threshold);
                break;
+       case SR_CONF_EXTERNAL_CLOCK:
+               *data = g_variant_new_boolean(devc->use_ext_clock);
+               break;
+       case SR_CONF_CLOCK_EDGE:
+               ext_clock_text = ext_clock_edges[devc->ext_clock_edge];
+               *data = g_variant_new_string(ext_clock_text);
+               break;
        default:
                return SR_ERR_NA;
        }
@@ -388,6 +404,7 @@ static int config_set(uint32_t key, GVariant *data,
        const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
 {
        struct dev_context *devc;
+       int idx;
        gdouble low, high;
 
        (void)cg;
@@ -405,6 +422,17 @@ static int config_set(uint32_t key, GVariant *data,
        case SR_CONF_VOLTAGE_THRESHOLD:
                g_variant_get(data, "(dd)", &low, &high);
                return set_voltage_threshold(devc, (low + high) / 2.0);
+       case SR_CONF_EXTERNAL_CLOCK:
+               devc->use_ext_clock = g_variant_get_boolean(data);
+               analyzer_set_ext_clock(devc->use_ext_clock, (ext_clock_edge_t)devc->ext_clock_edge);
+               break;
+       case SR_CONF_CLOCK_EDGE:
+               idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_edges));
+               if (idx < 0)
+                       return SR_ERR_ARG;
+               devc->ext_clock_edge = (ext_clock_edge_t)idx;
+               analyzer_set_ext_clock(devc->use_ext_clock, devc->ext_clock_edge);
+               break;
        default:
                return SR_ERR_NA;
        }
@@ -444,6 +472,10 @@ static int config_list(uint32_t key, GVariant **data,
                devc = sdi->priv;
                *data = std_gvar_tuple_u64(0, devc->max_sample_depth);
                break;
+       case SR_CONF_CLOCK_EDGE:
+               *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_edges));
+               break;
+
        default:
                return SR_ERR_NA;
        }

diff --git a/src/hardware/zeroplus-logic-cube/protocol.c b/src/hardware/zeroplus-logic-cube/protocol.c
index 37fcbdcc2eb04d09d3c15a8f4f18736fcef8fca0..430e3fd72cd504054fa1bb116e4377ecbe927f99 100644 (file)
--- a/src/hardware/zeroplus-logic-cube/protocol.c
+++ b/src/hardware/zeroplus-logic-cube/protocol.c
@@ -20,6 +20,7 @@
 #include <config.h>
 #include <math.h>
 #include "protocol.h"
+#include "analyzer.h"
 
 SR_PRIV size_t get_memory_size(int type)
 {

diff --git a/src/hardware/zeroplus-logic-cube/protocol.h b/src/hardware/zeroplus-logic-cube/protocol.h
index b0c358be09923a61a86b2ef049d42b75a7a23eb8..d2daf4a962bb3e75bee30e89e74a0473fc870df4 100644 (file)
--- a/src/hardware/zeroplus-logic-cube/protocol.h
+++ b/src/hardware/zeroplus-logic-cube/protocol.h
@@ -26,10 +26,14 @@
 #include <libusb.h>
 #include <libsigrok/libsigrok.h>
 #include "libsigrok-internal.h"
-#include "analyzer.h"
 
 #define LOG_PREFIX "zeroplus-logic-cube"
 
+typedef enum {
+       LAPC_CLOCK_EDGE_RISING,
+       LAPC_CLOCK_EDGE_FALLING,
+} ext_clock_edge_t;
+
 struct zp_model;
 struct dev_context {
        uint64_t cur_samplerate;
@@ -42,6 +46,8 @@ struct dev_context {
        uint64_t capture_ratio;
        double cur_threshold;
        const struct zp_model *prof;
+       gboolean use_ext_clock;
+       ext_clock_edge_t ext_clock_edge;
 };
 
 SR_PRIV size_t get_memory_size(int type);