]> sigrok.org Git - libsigrokdecode.git/commitdiff
unfinished update to onewire protocol decoder
authorUwe Hermann <redacted>
Tue, 3 Jul 2012 23:19:35 +0000 (01:19 +0200)
committerUwe Hermann <redacted>
Tue, 3 Jul 2012 23:50:44 +0000 (01:50 +0200)
configure.ac
decoders/Makefile.am
decoders/onewire/onewire.py

index 7bb760fc7358941083fa52dab7ae8a2286725b5c..abc2a37dacafd85e26dc8fcb9ad00aaa927b7450 100644 (file)
@@ -171,6 +171,7 @@ AC_CONFIG_FILES([Makefile
                 decoders/usb/Makefile
                 decoders/usb_signalling/Makefile
                 decoders/usb_protocol/Makefile
+                decoders/onewire/Makefile
                ])
 
 AC_OUTPUT
index 9f3f269e9d7747356df296e584daeb342460a4f3..3e3ff533f2fa6a88b5bc510c92808a1d66167ed6 100644 (file)
@@ -42,5 +42,6 @@ SUBDIRS = \
        uart_dump \
        usb \
        usb_signalling \
-       usb_protocol
+       usb_protocol \
+       onewire
 
index 38cc0b86bef59fc613c06228e44451d4c360e85f..92cc7dc48b725f4cc332b12d913a2be6a818c499 100644 (file)
@@ -94,7 +94,7 @@ class Decoder(srd.Decoder):
         pass
 
     def decode(self, ss, es, data):
-        for (self.samplenum, (owr, pwr)) in data:
+        for (self.samplenum, owr) in data:
 
             # Data link layer
 
@@ -133,7 +133,7 @@ class Decoder(srd.Decoder):
                     if (self.lnk_bit) :  self.lnk_state = 'WAIT FOR FALLING EDGE'
                     else              :  self.lnk_state = 'WAIT FOR RISING EDGE'
             else:
-                raise Exception('Invalid lnk_state: %s' % self.lnk_state)
+                raise Exception('Invalid lnk_state: %d' % self.lnk_state)
 
             # Network layer
             
@@ -149,10 +149,8 @@ class Decoder(srd.Decoder):
                     self.net_cnt = self.net_cnt + 1
                     self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
                     if (self.lnk_cnt == 8):
-                        self.put(self.startsample, self.samplenum,
-                                 self.out_proto, ['LNK: BYTE', self.lnk_byte])
-                        self.put(self.startsample, self.samplenum, self.out_ann,
-                                 [ANN_DEC, ['LNK: BYTE: ' + self.lnk_byte]])
+                        self.put(self.startsample, self.samplenum, self.out_proto, ['LNK: BYTE', self.lnk_byte])
+                        self.put(self.startsample, self.samplenum, self.out_ann  , ['LNK: BYTE', self.lnk_byte])
                         if   (self.net_cmd == 0x33):
                             # READ ROM
                             break
@@ -179,9 +177,9 @@ class Decoder(srd.Decoder):
                     #
                     break
                 else:
-                    raise Exception('Invalid net_state: %s' % self.net_state)
+                    raise Exception('Invalid net_state: %d' % self.net_state)
             elif not (self.lnk_event == "NONE"):
-                raise Exception('Invalid net_event: %s' % self.net_event)
+                raise Exception('Invalid net_event: %d' % self.net_event)