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parallel: add option to sample data on either clock edge
authorGerhard Sittig <redacted>
Sat, 7 Nov 2020 13:47:21 +0000 (14:47 +0100)
committerGerhard Sittig <redacted>
Wed, 11 Nov 2020 18:31:47 +0000 (19:31 +0100)
commite2317ec49b8b04c7f8b3358c2e9c264de4280539
treebde678ecc8ce98679d8086799a3fa1eb42019d3ftree | snapshot
parent615f86f6bf7f7166f2975c9efe7e727bf2b65734commit | diff
parallel: add option to sample data on either clock edge

Add 'either' as another choice in addition to rising and falling clock
edge. This is useful since parallel busses exist which communicate at
double data rate (DDR).

Unobfuscate the mapping between displayed option text and .wait()
condition codes while we are here.
decoders/parallel/pd.py diff | blob | blame | history
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