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(parent: 0e1a7fe)
saleae-logic16: Recognize FPGA FIFO overflow status
authorMarcus Comstedt <redacted>
Sun, 17 Aug 2014 12:20:01 +0000 (14:20 +0200)
committerMarcus Comstedt <redacted>
Sun, 17 Aug 2014 14:24:14 +0000 (16:24 +0200)
commit7754fb4d931013f520f85aa8cbef3bcd491e2599
treeb59abac1feaa3b9dbebf871bc520e0e75549afeetree | snapshot
parent0e1a7fe91a9132ad586337bdd29d93eff4344eddcommit | diff
saleae-logic16: Recognize FPGA FIFO overflow status
src/hardware/saleae-logic16/protocol.c diff | blob | blame | history
Hardware access and backend lib