kingst-la2016: keep FPGA active after device close

kingst-la2016: keep FPGA active after device close

When the sigrok driver closes as the application shuts down, acquisition
of logic input channels will have completed. Generation of PWM signals
on output channels can be desirable to keep up. Do not de-initialize the
FPGA hardware in the close code path. Which allows to configure PWM by
means of sigrok-cli and use the signals between program invocations that
reconfigure the generator. Users can always disable channels before the
application shuts down if they prefer to. Similar use was seen with PSUs.
Make this approach a compile time option.