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input/vcd: Add parsing support for SV 'logic' type
author7FM <redacted>
Thu, 13 Jan 2022 21:33:51 +0000 (22:33 +0100)
committerSoeren Apel <redacted>
Wed, 16 Oct 2024 23:02:42 +0000 (01:02 +0200)
commit47a98d305c6ad9b38c302618d864f1e77e9f036a
tree893286cd50d9c88964fd36021f33f26283b90933tree | snapshot
parent02c51d8a5f71152a5b230fc463719c13c9404f44commit | diff
input/vcd: Add parsing support for SV 'logic' type

logic is a SystemVerilog data type which is an extension of Verilog.
The relevant specification is contained in IEEE 1800-2017.
src/input/vcd.c diff | blob | blame | history
Hardware access and backend lib