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can: introduce clock synchronization (simple implementation)
authorGerhard Sittig <redacted>
Sun, 2 Jul 2017 10:39:08 +0000 (12:39 +0200)
committerUwe Hermann <redacted>
Tue, 4 Jul 2017 10:01:04 +0000 (12:01 +0200)
commit45a5088085c07c862549ad820d752a46ef0e0c76
tree6ff69adb5c9bf370fe8baa07a05e2697f1bf1525tree | snapshot
parent300f9194250913babbd57d5eccc2ceccf9010785commit | diff
can: introduce clock synchronization (simple implementation)

Check for falling edges (i.e. changes to dominant state) between bits of
a CAN frame, and adjust subsequent bit slots' sample points accordingly.
This is a simple implementation which could get improved later. But it
improves the decoder's reliability when the input signal's rate differs
from the nominal rate.

This fixes bug #990.

Reported-By: PeterMortensen via IRC
decoders/can/pd.py diff | blob | blame | history
Protocol decoder lib