uart: handle zero stop bits configuration

uart: handle zero stop bits configuration

Use common code to advance internal state during UART frame inspection.
This reduces redundancy, and improves robustness. Data bits collectors
need not worry about the optional presence of subsequent fields (parity,
stop bits, both can be absent).

Improve the separation of implementation details of the lower layer UART
frame decoding from upper layer protocol handling. Concentrate the post
processing of UART frames, BREAK and IDLE conditions in the source, and
keep the ss/es determination at the caller which detected the condition
by arbitrary means.

This unbreaks the decoder's operation when 0 stop bits are configured.
The implementation still assumes that the line goes idle between frames
even when zero stop bits are configured. Strictly speaking this decoder
now copes with traffic that uses "less than half a stop bit".