input/vcd: unbreak U and - values for single bit input data

input/vcd: unbreak U and - values for single bit input data

The previous implementation already mapped L/H/U/- literals for input
data values to the 0/1/0/0 logic levels which sigrok can handle. But
missed these literals in the condition which dispatches real/integer,
bit vector, and single bit data types. Which made VCD import fail for
some of the files in the SpinalWorkshop repo.

Extend the test condition for single bit values. This unbreaks the
import of the Apb3TimerTester.vcd and ApbPwmTester.vcd files, which
contained phrases like these:

  ...
  $var reg 1 % io_apb_pwrite $end
  ...
  #0
  bUUUUUUUU !
  b0 "
  0#
  1$
  U%

and

  ...
  $var reg 8 # io_apb_paddr[7:0] $end
  $var reg 1 $ io_apb_pwrite $end
  ...
  #0
  b0 !
  0"
  b-------- #
  -$
  b-------------------------------- %
  b00000000000000000000000000000000 &
  1'