Bug 218

Summary: Rational vdiv and timebase arguments are rejected unless an exact match.
Product: libsigrok Reporter: Martin Ling <martin-sigrokbugs>
Component: Driver: rigol-dsAssignee: Nobody <nobody>
Status: CONFIRMED ---    
Severity: normal CC: a-sigrok.org, stefan.bruens
Priority: Normal    
Version: unreleased development snapshot   
Target Milestone: ---   
Hardware: All   
OS: All   

Description Martin Ling 2013-12-18 03:33:38 CET
Rational input values for vdiv and timebase are checked against the supported values exactly. If the caller uses normalised fractions this will usually fail, e.g. for vdiv = 100mV, (1, 10) will be given but only (100, 1000) would match.

A reusable function implementing rational equality checks would be useful here.
Comment 1 Stefan BrĂ¼ns 2016-05-17 17:53:04 CEST
libsigrok now has sr_rational_eq

Comment 2 Valentin Ochs 2018-05-27 17:48:34 CEST
All supported devices accept a real value for vdiv settings. Maybe we should just check that the value is in range, and then pass it on?