Bug 1021

Summary:	pipistrello-ols driver should support loading the FPGA with required "gateware"
Product:	libsigrok	Reporter:	Tim 'mithro' Ansell <mithro>
Component:	Driver: pipistrello-ols	Assignee:	Nobody <nobody>
Status:	CONFIRMED ---
Severity:	normal	CC:	Gerhard.Sittig
Priority:	Normal
Version:	unreleased development snapshot
Target Milestone:	---
Hardware:	All
OS:	All

Description Tim 'mithro' Ansell 2017-09-03 22:51:22 CEST

Would be really nice if the pipistrello-ols driver could load the pipistrello with the required FPGA gateware.

The gateware is open source, so it shouldn't be an issue include it in sigrok.

It looks like other drivers already support loading FPGA gateware?

Comment 1 Gerhard Sittig 2017-09-17 12:31:28 CEST

I'd oppose such a "feature".  There is the valid and straight forward case of 
sigrok downloading firmware to volatile memory for devices which assume such 
a use (like FX2, Asix Sigma, and others).  Flashing firmware to permanent 
memory is rather different.  As is using a separate programming interface 
like JTAG before connecting to the regular means of communication to the 
device.  It would add complexity and involve dependencies that libsigrok 
should not have IMO.  Capture devices should either be configured already 
for acquisition, or provide a regular means of volatile programming if they 
lack persistent memory.

Also keep in mind that drivers will probe devices and optionally load firmware 
without the user's explicit request, like bus scans and feature detection as 
the software starts up.  Users will "thank" you if the driver keeps flashing 
the devices' permanent memory just because some libsigrok using application 
happens to start while the device is connected to the machine.  I feel that 
permanently flashing firmware to a device should be an explicit activity 
that's under the user's control.

Comment 2 Tim 'mithro' Ansell 2017-09-17 19:11:28 CEST

I'm not suggesting that sigrok "flash" the pipistrello or in anyway permanently modify it.

The pipistrello is perfectly capable of loading a design into the FPGA that goes away after power cycle (infact this is the normal mode of operation while doing development). This is identical to "volitile memory" behaviour you describe.

I think this should probably only happen after a user has selected the device to use. Detecting a pipistrello (scanning and such) can be done without needing to do the load.