Difference between revisions of "Sysclk LWLA1034"

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(Link to correct item on AliExpress)
 
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| image            = [[File:Sysclk lwla1034 mugshot.png|180px]]
| image            = [[File:Sysclk lwla1034 mugshot.png|180px]]
| name            = Sysclk LWLA1034
| name            = Sysclk LWLA1034
| status          = in progress
| status          = supported
| source_code_dir  =  
| source_code_dir  = sysclk-lwla
| channels        = 34
| channels        = 34
| samplerate      = 125MHz (max)
| samplerate      = 125MHz (max)
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| memory          = 256Kbit/channel
| memory          = 256Kbit/channel
| compression      = RLE
| compression      = RLE
| website          = [http://item.taobao.com/item.htm?id=19834430293 taobao.com]
| website          = [http://www.aliexpress.com/item/free-shipping-New-arrival-Powerful-100MHz-34-channels-LA1034-Logic-Analyzer-Timing-State-Logic-Analyzer/1227957767.html aliexpress.com]
}}
}}


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* Cypress CY7C68013A-56 (FX2) USB interface chip
* Cypress CY7C68013A-56 (FX2) USB interface chip
* Cypress 256k×36 SRAM (likely a [http://www.cypress.com/?mpn=CY7C1361C-133AXC CY7C1361C-133AXC] or similar)
* Cypress 256k×36 SRAM (likely a [http://www.cypress.com/?mpn=CY7C1361C-133AXC CY7C1361C-133AXC] or similar)
* STC15F104E 8051-based microcontroller


The not-installed 10-pin connector between the USB socket and the large capacitor seems to connect to the JTAG pins of the FPGA.
The not-installed 10-pin connector between the USB socket and the large capacitor seems to connect to the JTAG pins of the FPGA.
Line 64: Line 65:
== Firmware ==
== Firmware ==


* The FX2 firmware appears to be loaded from an EEPROM on the board, so that the final USB device descriptor is immediately available on power-up.
We have received permission from the vendor to distribute the FPGA bitstreams with sigrok. Thus, the bitstreams are now included in the sigrok-firmware module.
* Endpoint 4 appears to be used exclusively for loading a new bitstream into the FPGA.
* Endpoint 2 is apparently used for sending commands to the FPGA firmware, with responses (if any) coming in from endpoint 6.


Reverse engineering of the vendor protocol is currently in progress. See [[Sysclk LWLA1034/Protocol]] for a documentation of the findings gathered so far.
* The FX2 firmware is loaded from an EEPROM on the board, so that the final USB device descriptor is immediately available on power-up.
* Endpoint 4 is used exclusively for loading a new bitstream into the FPGA.
* Endpoint 2 is used for sending commands to the FPGA firmware, with responses (if any) coming in from endpoint 6.
 
Reverse engineering of the vendor's custom protocol has been completed. See [[Sysclk LWLA1034/Protocol]] for the documentation.


== Resources ==
== Resources ==
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[[Category:Device]]
[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Logic analyzer]]
[[Category:In progress]]
[[Category:Supported]]

Latest revision as of 23:27, 28 February 2014

Sysclk LWLA1034
Sysclk lwla1034 mugshot.png
Status supported
Source code sysclk-lwla
Channels 34
Samplerate 125MHz (max)
Samplerate (state) ?
Triggers 34 + extern
Min/max voltage 0-5V
Threshold voltage ?
Memory 256Kbit/channel
Compression RLE
Website aliexpress.com

The Sysclk LWLA1034 is a USB-based, 34-channel logic analyzer with up to 125MHz sampling rate.

See Sysclk LWLA1034/Info for more details (such as lsusb -v output) about the device.

Hardware

  • Altera EP2C5Q208C8N (Cyclone II) FPGA
  • Cypress CY7C68013A-56 (FX2) USB interface chip
  • Cypress 256k×36 SRAM (likely a CY7C1361C-133AXC or similar)
  • STC15F104E 8051-based microcontroller

The not-installed 10-pin connector between the USB socket and the large capacitor seems to connect to the JTAG pins of the FPGA.

Photos

(Note: The yellow/greenish markings weren't there, they're added by the photographer)

PCB for another device:

Software

Sysclk lwla1034 software.png

Firmware

We have received permission from the vendor to distribute the FPGA bitstreams with sigrok. Thus, the bitstreams are now included in the sigrok-firmware module.

  • The FX2 firmware is loaded from an EEPROM on the board, so that the final USB device descriptor is immediately available on power-up.
  • Endpoint 4 is used exclusively for loading a new bitstream into the FPGA.
  • Endpoint 2 is used for sending commands to the FPGA firmware, with responses (if any) coming in from endpoint 6.

Reverse engineering of the vendor's custom protocol has been completed. See Sysclk LWLA1034/Protocol for the documentation.

Resources