Difference between revisions of "Saleae Logic16"
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[[File:Saleae Logic16.jpg|thumb|right|Saleae Logic16, front]] | [[File:Saleae Logic16.jpg|thumb|right|Saleae Logic16, front]] | ||
The [http://www.saleae.com/logic16/ Saleae Logic16] is a 16-channel | The [http://www.saleae.com/logic16/ Saleae Logic16] is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels). | ||
The case requires a Torx T5 screwdriver to open. | The case requires a '''Torx T5''' screwdriver to open. | ||
See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | ||
See [[Saleae Logic]] for the predecessor product of the Saleae Logic16. | |||
== Hardware == | == Hardware == | ||
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== Protocol == | == Protocol == | ||
'''Sample format''': | |||
The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows: | |||
'''<span style="background-color: yellow">0xLL 0xLL 0xMM 0xMM 0xNN 0xNN</span> <span style="background-color: cyan">0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR</span> ...''' | |||
In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again. | |||
The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate). | |||
== Resources == | == Resources == | ||
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* [http://downloads.saleae.com/Logic+Guide.pdf Manual] | * [http://downloads.saleae.com/Logic+Guide.pdf Manual] | ||
* [http://www.saleae.com/downloads Vendor software] | * [http://www.saleae.com/downloads Vendor software] | ||
* [http://community.saleae.com/ SDKs] | |||
[[Category:Device]] | [[Category:Device]] | ||
[[Category:Logic analyzer]] | [[Category:Logic analyzer]] | ||
[[Category:Planned]] | [[Category:Planned]] | ||
Revision as of 02:08, 23 January 2013
The Saleae Logic16 is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).
The case requires a Torx T5 screwdriver to open.
See Saleae Logic16/Info for more details (such as lsusb -vvv output) about the device.
See Saleae Logic for the predecessor product of the Saleae Logic16.
Hardware
- Xilinx XC3S200A 200K gate FPGA
- Cypress CY7C68013A-56PVXC (FX2LP) USB interface chip
Photos
Device, front
Device, bottom
PCB, top
PCB, bottom
Protocol
Sample format:
The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:
0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...
In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.
The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).