Difference between revisions of "CWAV USBee SX"
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Uwe Hermann (talk | contribs) m |
Uwe Hermann (talk | contribs) m |
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| samplerate_state = — | | samplerate_state = — | ||
| triggers = none (SW-only) | | triggers = none (SW-only) | ||
| voltages = | | voltages = max. 5.5V | ||
| threshold = Fixed: VIH=1.4V, VIL=0.8V | |||
| memory = none | | memory = none | ||
| compression = none | | compression = none | ||
Revision as of 10:19, 27 April 2013
 | |
| Status | supported |
|---|---|
| Source code | fx2lafw |
| Channels | 8 |
| Samplerate | 24MHz |
| Samplerate (state) | — |
| Triggers | none (SW-only) |
| Min/max voltage | max. 5.5V |
| Threshold voltage | Fixed: VIH=1.4V, VIL=0.8V |
| Memory | none |
| Compression | none |
| Website | usbee.com |
The USBee SX is a USB-based, 8-channel logic analyzer (and signal generator) with up to 24MHz sampling rate.
In sigrok, we use the open-source fx2lafw firmware for this logic analyzer.
See CWAV USBee SX/Info for some more details (such as lsusb -vvv output) on the device.
Hardware
- Main chip: Cypress CY7C68013A-56PVXC (FX2LP)
- Note: Older versions used the Cypress CY7C68013-56PVC (FX2), which is different in some ways (e.g. less SRAM)
- 3.3V voltage regulator: ST LD33
- I2C EEPROM: Microchip 24LC01B
- Crystal: 24MHz
Photos
New version with Cypress CY7C68013A (FX2LP):
Device, front
Device, back
Device, open
PCB, front
PCB, back
Old version with Cypress CY7C68013 (FX2):
Device, front
Device, back
PCB, front
PCB, back
"USBee ZX" marking
Protocol
Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.
However, for those interested in this, someone else has already decoded most of it.