sigrok - User contributions [en]

Saleae Logic16

2015-07-02T13:41:31Z

Marcus Comstedt: /* Hardware */ Add FPGA connections

{{Infobox logic analyzer
| image = [[File:Saleae Logic16 bottom.png|180px]]
| name = Saleae Logic16
| status = supported
| source_code_dir = saleae-logic16
| channels = 3/6/9/16
| samplerate = 100/50/32/16MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://www.saleae.com/logic16/ saleae.com]
}}

The '''Saleae Logic16''' is a USB-based, 16-channel logic analyzer with 100/50/32/16MHz sampling rate (at 3/6/9/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''Ultralow capacitance ESD protection''': 4x [http://www.st.com/web/catalog/sense_power/FM114/CL1137/SC1490/PF109008 ST DVIULC6-4SC6] ([http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00065974.pdf datasheet])
* '''2Kbit I2C EEPROM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010774 Microchip 24AA02] ([http://ww1.microchip.com/downloads/en/DeviceDoc/21709J.pdf datasheet]) (marking: "B2TH", starts with "B2" always, the last 2 characters are a "traceability code")
* '''2.5MHz, 1.5A synchronous step down switching regulator (1.2V)''': [http://www.semtech.com/power-management/switching-regulators/sc189 Semtech SC189] ([http://www.semtech.com/images/datasheet/sc189.pdf datasheet]) (marking: "189C")
* '''2.5MHz, 1.5A synchronous step down switching regulator (3.3V)''': [http://www.semtech.com/power-management/switching-regulators/sc189 Semtech SC189] ([http://www.semtech.com/images/datasheet/sc189.pdf datasheet]) (marking: "189Z")
* '''?''': 2x Unknown 3-pin IC. Markings: "72Y7".

'''Pinouts and connections:'''

'''JTAG header (FPGA):'''

The '''J3''' pin header is a JTAG connector wired to the FPGA. The pins are (from left to right, the right-most pin, pin number 1, is square):

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!5
!4
!3
!2
!1

|-
| GND
| TMS
| TCK
| TDO
| TDI

|}

'''Testpoints:'''

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!T1
!T2
!T3

|-
| 1.2V
| 3.3V
| GND (FX2)

|}

'''Cypress FX2:'''


{{chip_56pin
| 1=(FPGA 15, IO_L05P_3) PD5
| 2=(FPGA 13, IO_L04N_3) PD6
| 3=(FPGA 10, IO_L03N_3) PD7
| 4=GND
| 5=(FPGA 90, IO_0) CLKOUT
| 6=VCC
| 7=GND
| 8=(FPGA 3, IO_L01P_3) RDY0/*SLRD
| 9=(FPGA 16, IO_L05N_3) RDY1/*SLWR
| 10=AVCC
| 11=(24MHz crystal) XTALOUT
| 12=(24MHz crystal) XTALIN
| 13=AGND
| 14=AVCC

| 15=(USB D+) DPLUS
| 16=(USB D-) DMINUS
| 17=AGND
| 18=VCC
| 19=GND
| 20=(FPGA 84, IO_L02N_0) *IFCLK
| 21=RESERVED
| 22=(EEPROM SCL) SCL
| 23=(EEPROM SDA) SDA
| 24=VCC
| 25=(FPGA 40, IO_L08P_2) PB0
| 26=(FPGA 78, IO_L01N_0) PB1
| 27=(FPGA 77, IO_L01P_0) PB2
| 28=(FPGA 49, IO_L10N_2) PB3

| 29=PB4 (FPGA 46, MOSI)
| 30=PB5 (FPGA 41, IO_L08N_2)
| 31=PB6 (FPGA 37, IO_L07N_2)
| 32=PB7 (FPGA 93, IO_L05P_0)
| 33=GND
| 34=VCC
| 35=GND
| 36=CTL0 (FPGA 94, IO_L05N_0)
| 37=CTL1 (FPGA 97, IP_0)
| 38=CTL2 (FPGA 100, PROG_B)
| 39=VCC
| 40=PA0 (FPGA 54, DONE)
| 41=PA1 (FPGA 48, INIT_B)
| 42=PA2 (FPGA 53, CCLK)

| 43=PA3 (FPGA 51, MISO)
| 44=PA4 (FPGA 98, IO_L06P_0)
| 45=PA5 (FPGA 85, IO_L03P_0)
| 46=PA6 (FPGA 30, IO_L04P_2)
| 47=PA7 (FPGA 9, IO_L03P_3)
| 48=GND
| 49=RESET# (3.3V via D2 (diode?))
| 50=VCC
| 51=*WAKEUP (3.3V)
| 52=PD0 (FPGA 6, IO_L02N_3)
| 53=PD1 (FPGA 4, IO_L01N_3)
| 54=PD2 (FPGA 5, IO_L02P_3)
| 55=PD3 (FPGA 44, IO_L09N_2)
| 56=PD4 (FPGA 12, IO_L04P_3)

}}


'''Other FPGA connections:'''

{| border="0" style="font-size: smaller" class="sigroktable"
|-
!28
|CH0
!52
|CH8
|-
!29
|CH1
!56
|CH9
|-
!32
|CH2
!57
|CH10
|-
!33
|CH3
!60
|CH11
|-
!34
|CH4
!61
|CH12
|-
!36
|CH5
!62
|CH13
|-
!43
|CH6
!64
|CH14
|-
!50
|CH7
!65
|CH15
|-
!73
|colspan="3"|LED (active low)
|}

== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
File:Saleae logic16 xilinx xc3s200a.jpg|Xilinx XC3S200A
File:Saleae logic16 cypress fx2lp.jpg|Cypress FX2LP
File:Saleae logic16 eeprom b2th.jpg|I2C EEPROM
File:Saleae logic16 dl46.jpg|ST DVIULC6-4SC6
File:Saleae logic16 189z 189c.jpg|Voltage regulators
File:Saleae logic16 72y7.jpg|72Y7

</gallery>

== Firmware ==

=== Firmware and FPGA bitstream usage ===

You can use the [http://sigrok.org/gitweb/?p=sigrok-util.git;a=tree;f=firmware/saleae-logic16 sigrok-fwextract-saleae-logic16] tool to extract (from the "Logic" Linux binary) the FX2 firmware and the FPGA bitstreams required for using the Saleae Logic16:

$ '''sigrok-fwextract-saleae-logic16 Logic'''
saved 5214 bytes to saleae-logic16-fx2.fw
saved 149516 bytes to saleae-logic16-fpga-18.bitstream
saved 149516 bytes to saleae-logic16-fpga-33.bitstream

Copy these files to the directory where your [[libsigrok]] installation expects them (usually '''/usr/local/share/sigrok-firmware''') and they will be found and used automatically by the libsigrok '''saleae-logic16''' driver.

=== Technical firmware details ===

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order.

See [[Saleae Logic16/Firmware]] for more details on the vendor firmware.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

{| border="0" style="font-size: smaller; white-space: nowrap;" class="alternategrey sigroktable"
!colspan="2"|Channel number configuration
|-
| 3 channels
| <tt>0x80 0x01 0x02 '''0x07''' 0x80 0x01 0x03 '''0x00'''</tt>
|-
| 6 channels
| <tt>0x80 0x01 0x02 '''0x3f''' 0x80 0x01 0x03 '''0x00'''</tt>
|-
| 9 channels
| <tt>0x80 0x01 0x02 '''0xff''' 0x80 0x01 0x03 '''0x01'''</tt>
|-
| 16 channels
| <tt>0x80 0x01 0x02 '''0xff''' 0x80 0x01 0x03 '''0xff'''</tt>
|}

{| border="0" style="font-size: smaller; white-space: nowrap;" class="alternategrey sigroktable"
!colspan="2"|Sampling frequency
|-
| 500kHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0xc7'''</tt>
|-
| 1MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x63'''</tt>
|-
| 2MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x31'''</tt>
|-
| 4MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x18'''</tt>
|-
| 5MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x13'''</tt>
|-
| 8MHz
| <tt>0x80 0x01 0x0a '''0x01''' 0x80 0x01 0x04 '''0x13'''</tt>
|-
| 10MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x09'''</tt>
|-
| 12.5MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x07'''</tt>
|-
| 16MHz
| <tt>0x80 0x01 0x0a '''0x01''' 0x80 0x01 0x04 '''0x09'''</tt>
|-
| 25MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x03'''</tt>
|-
| 32MHz
| <tt>0x80 0x01 0x0a '''0x01''' 0x80 0x01 0x04 '''0x04'''</tt>
|-
| 40MHz
| <tt>0x80 0x01 0x0a '''0x01''' 0x80 0x01 0x04 '''0x03'''</tt>
|-
| 50MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x01'''</tt>
|-
| 80MHz
| <tt>0x80 0x01 0x0a '''0x01''' 0x80 0x01 0x04 '''0x01'''</tt>
|-
| 100MHz
| <tt>0x80 0x01 0x0a '''0x00''' 0x80 0x01 0x04 '''0x00'''</tt>
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Supported]]

Saleae Logic16/Firmware

2015-04-22T19:34:38Z

Marcus Comstedt: Updated to contain renumbering of variables and bits in new FPGA bitstream

The following information is related to the vendor firmware included with the version 1.1.15 of the vendor application "Logic".

== Interrupt handlers ==

The following interrupt handlers are installed. If the address is absent, it means the handler just returns (RETI) without performing any action. Addresses in red is for the new firmware version (vendor software version 1.1.34).

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Handler
!Address
|-
| RESET
| 0x0000
|-
| TF2
| 0x0e65
|-
| RESUME
| 0x002e
|-
| SUDAV
| 0x0ae8
|-
| SOF
| 0x13d2 0x13d6
|-
| SUTOK
| 0x13bf 0x13c3
|-
| SUSPEND
| 0x13aa 0x13ae
|-
| USB_RESET
| 0x130b 0x130f
|-
| HISPEED
| 0x12df 0x12e3
|-
| EP0ACK
|
|-
| EP0_IN
|
|-
| EP0_OUT
|
|-
| EP1_IN
|
|-
| EP1_OUT
| 0x115d 0x1161
|-
| EP2
| 0x11a2 0x11a6
|-
| EP4
|
|-
| EP6
|
|-
| EP8
|
|-
| IBN
|
|-
| EP0PING
|
|-
| EP1PING
|
|-
| EP2PING
|
|-
| EP4PING
|
|-
| EP6PING
|
|-
| EP8PING
|
|-
| ERRLIMIT
|
|-
| EP2ISOERR
|
|-
| EP4ISOERRF
|
|-
| EP6ISOERR
|
|-
| EP8ISOERRF
|
|-
| EP2PF
|
|-
| EP4PF
|
|-
| EP6PF
|
|-
| EP8PF
|
|-
| EP2EF
|
|-
| EP4EF
|
|-
| EP6EF
|
|-
| EP8EF
|
|-
| EP2FF
| 0x11e7 0x11eb
|-
| EP4FF
|
|-
| EP6FF
|
|-
| EP8FF
|
|-
| GPIFDONE
|
|-
| GPIFWF
|
|}

=== Endpoint 1 OUT (EP1_OUT) handler ===

After decrypting the OUT packet, processing of the packet proceeds depending on the first byte of the packet, which selects the operation. After the operation, any resulting IN packet will be encrypted before submitting it to the host.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Byte
!Handler
!Operation
|-
| 1
| 0x14f
| Configure endpoints for quad-buffered bulk FIFO operation, and trigger a GPIF read on EP2.
|-
| 2
| 0x157
| Abort the GPIF. In the new firmware, also reconfigures the endpoints like operation 1.
|-
| 6
| 0x15f 0x162
| Write data to EEPROM with I²C address 1010000 (0x50) in single byte addressing mode. The second and third byte contain a fixed magic cookie of '''0x42 0x55'''. The fourth byte contains the single byte address. The fifth byte contains the number of bytes to write (1-58). The rest of the packet contains the data to write.
|-
| 7
| 0x1b3 0x1b6
| Read data from EEPROM with I²C address 1010000 (0x50) in single byte addressing mode. The second and third byte contain a fixed magic cookie of '''0x33 0x81'''. The fourth byte contains the single byte address. The fifth byte contains the number of bytes to read (1-64). The data will be available as an IN transfer.
|-
| 0x7a
| 0x309 0x30c
| Upload the sine table for LED flashing. The second byte contains the offset to start writing at, and the third byte the number of bytes to write. A maximum of 61 bytes can be uploaded per packet, so two packets are needed to write the entire table.
|-
| 0x7b
| 0x346 0x349
| Enable or disable LED flashing. The second byte of the packet is a bool indicating if LED flashing should be enabled. The following bytes are only used if LED flashing is enabled, but are always transmitted. If flashing is enabled, the LED brighness will periodically be set from the sine table. Byte 3 and 4 of the packet are the Timer 2 reload value, in little endian format. Byte 5 is a software clock divisor. The pointer in the sine table will be advanced by one every '''(0x10000 - RELOAD) * (DIV + 1) / 4000000''' seconds. Byte 6 is a boolean indicating whether to repeat the waveform (1) or stop at the end of the first period (0).
|-
| 0x7c
| 0x282 0x285
| Re-renumerate; return control to the builtin bootloader.
|-
| 0x7d
| 0x2aa 0x2ad
| Abort the GPIF. The second byte of the packet is returned complemented in an IN transfer, as acknowledgement.
|-
| 0x7e
| 0x2cf 0x2d2
| Disable LED flashing, configure the GPIF, and prepare the FPGA for bitstream upload by pulsing '''PROG_B''' and then waiting for '''INIT_B'''.
|-
| 0x7f
| 0x2e4 0x2e7
| Disable LED flashing, transmit N (1-62) bytes of bitstream on the FPGA '''DIN''' pin, clocked by '''CCLK'''. The second byte of the packet encodes N.
|-
| 0x80
| 0x205 0x208
| Transmit N (1-31) 16-bit words to the FPGA. The second byte of the packet encodes N. Data is sent on '''PA6''', MSB-first, with rising edges of '''PA5''' to clock the bits out. During each word transfer, '''PA4''' is held low. The most significant bit (b15) of each word must be 0.
|-
| 0x81
| 0x23b 0x23e
| Perform N (1-31) write-read transactions to the FPGA. The second byte of the packet encodes N. Each transaction consists of 8 bits (from the out packet) being transmitted on '''PA6''', like for the 0x80 operation above, and then 8 bits being received on '''PA7'''. N bytes will be available for an IN transfer afterwards. The most significant bit (b7) of each byte to send must be 0, but is actually transmitted as a 1 (to indicate read operation). '''PA7''' is polled immediately after the falling edge of '''PA5'''. '''PA4''' is held low during each write-read transaction.
|-
| 0x82
| 0x3a3 0x3a6
| Read the REVID register. 16 bits of '''REVID''' data will be available for an IN transfer.
|-
| others
| 0x3c7 0x3ca
| Do nothing
|}

==== Command 0x7e waveform ====

[[File:Logic16 FW Command 0x7e Waveform.svg]]

==== Command 0x7f waveform ====

[[File:Logic16 FW Command 0x7f Waveform.svg]]

==== Command 0x80 waveform ====

[[File:Logic16 FW Command 0x80 Waveform.svg]]

==== Command 0x81 waveform ====

[[File:Logic16 FW Command 0x81 Waveform.svg]]

== XDATA variables ==

The following variables are stored in the 8K "external" code/data memory, after the firmware code.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!rowspan="2"|Address
!colspan="2"|Init data in FW
!rowspan="2"|Contents
|-
!Address
!Value
|-
| 0x1f00-0x1f7f
| 0x8d6-0x955
|
| WAVEDATA
|-
| 0x1f80
| 0x981
| 0xe0
| GPIFREADYCFG
|-
| 0x1f81
| 0x982
| 0x10
| GPIFCTLCFG
|-
| 0x1f82
| 0x983
| 0x00
| GPIFIDLECS
|-
| 0x1f83
| 0x984
| 0x05
| GPIFIDLECTL
|-
| 0x1f84
| 0x985
| 0xee
| ?
|-
| 0x1f85
| 0x986
| 0x50
| GPIFWFSELECT
|-
| 0x1f86
| 0x987
| 0x00
| GPIFREADYSTAT
|-
| 0x1f87
| 0x95a
| 0x00
| FLOWSTATE
|-
| 0x1f88
| 0x95b
| 0x00
| FLOWLOGIC
|-
| 0x1f89
| 0x95c
| 0x00
| FLOWEQ0CTL
|-
| 0x1f8a
| 0x95d
| 0x00
| FLOWEQ1CTL
|-
| 0x1f8b
| 0x95e
| 0x00
| FLOWHOLDOFF
|-
| 0x1f8c
| 0x95f
| 0x00
| FLOWSTB
|-
| 0x1f8d
| 0x960
| 0x00
| FLOWSTBEDGE
|-
| 0x1f8e
| 0x961
| 0x00
| FLOWSTBHPERIOD
|-
| 0x1f8f-0x1faa
| 0x962-0x97d
| 0x00
| ?
|-
| 0x1fab-0x1fea
|
|
| 64 byte sine table for LED flashing
|}

=== WAVEDATA ===

The following data is loaded into WAVEDATA on bootup, and whenever operation 0x7e is performed:

==== Waveform descriptor 0 ====

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!State
!Length/Branch
!Opcode
!Output
!Logic
!Operation
!NEXT
!DATA
!CTL2
!CTL1
!CTL0
|-
| 0
| 0x81
| 0x01
| 0x05
| 0x70
| if FF or RDY0 then 0 (ReExec) else 1
| 0
| 0
| 1
| 0
| 1
|-
| 1
| 0xB8
| 0x07
| 0x04
| 0x2D
| if TC expired then 7 else 0
| 1
| 1
| 1
| 0
| 0
|-
| 2
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 3
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 4
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 5
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 6
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|}

==== Waveform descriptor 1-3 ====

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!State
!Length/Branch
!Opcode
!Output
!Logic
!Operation
!NEXT
!DATA
!CTL2
!CTL1
!CTL0
|-
| 0-6
| 0x01
| 0x00
| 0x05
| 0x00
| Delay 1
| 0
| 0
| 1
| 0
| 1
|}

== FPGA variables ==

The following variables can be read and written by the host using operations 0x81 and 0x80 (red numbers indicate variable and bit numbers in the new version bitstreams):

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
! style="width: 4em;" | Address
! style="width: 3em;" | Bit
! Contents
|-
| 0x00 0x07
|
| '''FPGA bitstream version''' (currently 0x10 0x13).
|-
| 0x01 0x0f
|
| '''Status and control'''.
|-
|
| 0 5
| Acquisition running
|-
|
| 1 3
| Update acquisition parameters(?)
|-
|
| 2
|
|-
|
| 3 4
|
|-
|
| 4
|
|-
|
| 5 0
| FIFO overflow
|-
|
| 6 2
|
|-
|
| 7
|

|-
| 0x02 0x01
|
| '''Channel select low'''. Each 1 bit in this byte enables one of the channels 0-7 for acquisition.
|-
| 0x03 0x06
|
| '''Channel select high'''. Each 1 bit in this byte enables one of the channels 8-15 for acquisition.
|-
| 0x04 0x0b
|
| '''Sampling rate divisor'''. Sample rate is the base clock divided by N+1, where N is the value in this register.
|-
| 0x05 0x05
|
| '''LED brightness'''. 0 = min (off), 0xff = max, 0x19 = dimmed.
|-
| 0x06 0x0e
|
| ?
|-
| 0x07 0x02
|
| ?
|-
| 0x08
|
| ? (Read on acquisition stop.)
|-
| 0x09
|
| ? (Read on acquisition stop.)
|-
| 0x0a 0x04
|
|
|-
|
| 0 2
| Sampling base clock select: 0 = 100MHz, 1 = 160MHz
|-
|
| 1
|
|-
|
| 2
|
|-
|
| 3
|
|-
|
| 4
|
|-
|
| 5
|
|-
|
| 6 7
|
|-
|
| 7 0
|

|-
| 0x0c 0x03
|
| ?
|}

== EEPROM layout ==

The Saleae Logic16 has a 256-byte I2C EEPROM with the following layout:

c0 a9 21 01 10 00 00 00 aa bb cc dd ee ff gg hh
xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Description:

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Bytes
!Description
|-
| style="background-color: orange" | 0
| '''0xc0''': FX2 "c0 load" mode, i.e. VID/PID/DID are loaded from EEPROM (but not firmware).
|-
| style="background-color: lime" | 1-2
| '''0x21a9''': USB vendor ID (VID).
|-
| style="background-color: green" | 3-4
| '''0x1001''': USB product ID (PID).
|-
| style="background-color: lightgreen" | 5-6
| '''0x0000''': USB device ID (DID).
|-
| style="background-color: brown" | 7
| '''0x00''': FX2 configuration byte (see FX2 TRM for details).
|-
| style="background-color: yellow" | 8-15
| A unique device identifier / serial number for this Logic16 (8 bytes).
|-
| style="background-color: cyan" | 16-31
| "Magic" values that are different for each Logic16 device (16 bytes).
|}

Saleae Logic16/Firmware

2015-04-17T21:16:45Z

Marcus Comstedt: Updated to contain changes in new firmware

The following information is related to the vendor firmware included with the version 1.1.15 of the vendor application "Logic".

== Interrupt handlers ==

The following interrupt handlers are installed. If the address is absent, it means the handler just returns (RETI) without performing any action. Addresses in red is for the new firmware version (vendor software version 1.1.34).

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Handler
!Address
|-
| RESET
| 0x0000
|-
| TF2
| 0x0e65
|-
| RESUME
| 0x002e
|-
| SUDAV
| 0x0ae8
|-
| SOF
| 0x13d2 0x13d6
|-
| SUTOK
| 0x13bf 0x13c3
|-
| SUSPEND
| 0x13aa 0x13ae
|-
| USB_RESET
| 0x130b 0x130f
|-
| HISPEED
| 0x12df 0x12e3
|-
| EP0ACK
|
|-
| EP0_IN
|
|-
| EP0_OUT
|
|-
| EP1_IN
|
|-
| EP1_OUT
| 0x115d 0x1161
|-
| EP2
| 0x11a2 0x11a6
|-
| EP4
|
|-
| EP6
|
|-
| EP8
|
|-
| IBN
|
|-
| EP0PING
|
|-
| EP1PING
|
|-
| EP2PING
|
|-
| EP4PING
|
|-
| EP6PING
|
|-
| EP8PING
|
|-
| ERRLIMIT
|
|-
| EP2ISOERR
|
|-
| EP4ISOERRF
|
|-
| EP6ISOERR
|
|-
| EP8ISOERRF
|
|-
| EP2PF
|
|-
| EP4PF
|
|-
| EP6PF
|
|-
| EP8PF
|
|-
| EP2EF
|
|-
| EP4EF
|
|-
| EP6EF
|
|-
| EP8EF
|
|-
| EP2FF
| 0x11e7 0x11eb
|-
| EP4FF
|
|-
| EP6FF
|
|-
| EP8FF
|
|-
| GPIFDONE
|
|-
| GPIFWF
|
|}

=== Endpoint 1 OUT (EP1_OUT) handler ===

After decrypting the OUT packet, processing of the packet proceeds depending on the first byte of the packet, which selects the operation. After the operation, any resulting IN packet will be encrypted before submitting it to the host.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Byte
!Handler
!Operation
|-
| 1
| 0x14f
| Configure endpoints for quad-buffered bulk FIFO operation, and trigger a GPIF read on EP2.
|-
| 2
| 0x157
| Abort the GPIF. In the new firmware, also reconfigures the endpoints like operation 1.
|-
| 6
| 0x15f 0x162
| Write data to EEPROM with I²C address 1010000 (0x50) in single byte addressing mode. The second and third byte contain a fixed magic cookie of '''0x42 0x55'''. The fourth byte contains the single byte address. The fifth byte contains the number of bytes to write (1-58). The rest of the packet contains the data to write.
|-
| 7
| 0x1b3 0x1b6
| Read data from EEPROM with I²C address 1010000 (0x50) in single byte addressing mode. The second and third byte contain a fixed magic cookie of '''0x33 0x81'''. The fourth byte contains the single byte address. The fifth byte contains the number of bytes to read (1-64). The data will be available as an IN transfer.
|-
| 0x7a
| 0x309 0x30c
| Upload the sine table for LED flashing. The second byte contains the offset to start writing at, and the third byte the number of bytes to write. A maximum of 61 bytes can be uploaded per packet, so two packets are needed to write the entire table.
|-
| 0x7b
| 0x346 0x349
| Enable or disable LED flashing. The second byte of the packet is a bool indicating if LED flashing should be enabled. The following bytes are only used if LED flashing is enabled, but are always transmitted. If flashing is enabled, the LED brighness will periodically be set from the sine table. Byte 3 and 4 of the packet are the Timer 2 reload value, in little endian format. Byte 5 is a software clock divisor. The pointer in the sine table will be advanced by one every '''(0x10000 - RELOAD) * (DIV + 1) / 4000000''' seconds. Byte 6 is a boolean indicating whether to repeat the waveform (1) or stop at the end of the first period (0).
|-
| 0x7c
| 0x282 0x285
| Re-renumerate; return control to the builtin bootloader.
|-
| 0x7d
| 0x2aa 0x2ad
| Abort the GPIF. The second byte of the packet is returned complemented in an IN transfer, as acknowledgement.
|-
| 0x7e
| 0x2cf 0x2d2
| Disable LED flashing, configure the GPIF, and prepare the FPGA for bitstream upload by pulsing '''PROG_B''' and then waiting for '''INIT_B'''.
|-
| 0x7f
| 0x2e4 0x2e7
| Disable LED flashing, transmit N (1-62) bytes of bitstream on the FPGA '''DIN''' pin, clocked by '''CCLK'''. The second byte of the packet encodes N.
|-
| 0x80
| 0x205 0x208
| Transmit N (1-31) 16-bit words to the FPGA. The second byte of the packet encodes N. Data is sent on '''PA6''', MSB-first, with rising edges of '''PA5''' to clock the bits out. During each word transfer, '''PA4''' is held low. The most significant bit (b15) of each word must be 0.
|-
| 0x81
| 0x23b 0x23e
| Perform N (1-31) write-read transactions to the FPGA. The second byte of the packet encodes N. Each transaction consists of 8 bits (from the out packet) being transmitted on '''PA6''', like for the 0x80 operation above, and then 8 bits being received on '''PA7'''. N bytes will be available for an IN transfer afterwards. The most significant bit (b7) of each byte to send must be 0, but is actually transmitted as a 1 (to indicate read operation). '''PA7''' is polled immediately after the falling edge of '''PA5'''. '''PA4''' is held low during each write-read transaction.
|-
| 0x82
| 0x3a3 0x3a6
| Read the REVID register. 16 bits of '''REVID''' data will be available for an IN transfer.
|-
| others
| 0x3c7 0x3ca
| Do nothing
|}

==== Command 0x7e waveform ====

[[File:Logic16 FW Command 0x7e Waveform.svg]]

==== Command 0x7f waveform ====

[[File:Logic16 FW Command 0x7f Waveform.svg]]

==== Command 0x80 waveform ====

[[File:Logic16 FW Command 0x80 Waveform.svg]]

==== Command 0x81 waveform ====

[[File:Logic16 FW Command 0x81 Waveform.svg]]

== XDATA variables ==

The following variables are stored in the 8K "external" code/data memory, after the firmware code.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!rowspan="2"|Address
!colspan="2"|Init data in FW
!rowspan="2"|Contents
|-
!Address
!Value
|-
| 0x1f00-0x1f7f
| 0x8d6-0x955
|
| WAVEDATA
|-
| 0x1f80
| 0x981
| 0xe0
| GPIFREADYCFG
|-
| 0x1f81
| 0x982
| 0x10
| GPIFCTLCFG
|-
| 0x1f82
| 0x983
| 0x00
| GPIFIDLECS
|-
| 0x1f83
| 0x984
| 0x05
| GPIFIDLECTL
|-
| 0x1f84
| 0x985
| 0xee
| ?
|-
| 0x1f85
| 0x986
| 0x50
| GPIFWFSELECT
|-
| 0x1f86
| 0x987
| 0x00
| GPIFREADYSTAT
|-
| 0x1f87
| 0x95a
| 0x00
| FLOWSTATE
|-
| 0x1f88
| 0x95b
| 0x00
| FLOWLOGIC
|-
| 0x1f89
| 0x95c
| 0x00
| FLOWEQ0CTL
|-
| 0x1f8a
| 0x95d
| 0x00
| FLOWEQ1CTL
|-
| 0x1f8b
| 0x95e
| 0x00
| FLOWHOLDOFF
|-
| 0x1f8c
| 0x95f
| 0x00
| FLOWSTB
|-
| 0x1f8d
| 0x960
| 0x00
| FLOWSTBEDGE
|-
| 0x1f8e
| 0x961
| 0x00
| FLOWSTBHPERIOD
|-
| 0x1f8f-0x1faa
| 0x962-0x97d
| 0x00
| ?
|-
| 0x1fab-0x1fea
|
|
| 64 byte sine table for LED flashing
|}

=== WAVEDATA ===

The following data is loaded into WAVEDATA on bootup, and whenever operation 0x7e is performed:

==== Waveform descriptor 0 ====

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!State
!Length/Branch
!Opcode
!Output
!Logic
!Operation
!NEXT
!DATA
!CTL2
!CTL1
!CTL0
|-
| 0
| 0x81
| 0x01
| 0x05
| 0x70
| if FF or RDY0 then 0 (ReExec) else 1
| 0
| 0
| 1
| 0
| 1
|-
| 1
| 0xB8
| 0x07
| 0x04
| 0x2D
| if TC expired then 7 else 0
| 1
| 1
| 1
| 0
| 0
|-
| 2
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 3
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 4
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 5
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 6
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|}

==== Waveform descriptor 1-3 ====

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!State
!Length/Branch
!Opcode
!Output
!Logic
!Operation
!NEXT
!DATA
!CTL2
!CTL1
!CTL0
|-
| 0-6
| 0x01
| 0x00
| 0x05
| 0x00
| Delay 1
| 0
| 0
| 1
| 0
| 1
|}

== FPGA variables ==

The following variables can be read and written by the host using operations 0x81 and 0x80:

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
! style="width: 4em;" | Address
! style="width: 3em;" | Bit
! Contents
|-
| 0x00
|
| '''FPGA bitstream version''' (currently 0x10).
|-
| 0x01
|
| '''Status and control'''.
|-
|
| 0
| Acquisition running
|-
|
| 1
| Update acquisition parameters(?)
|-
|
| 2
|
|-
|
| 3
|
|-
|
| 4
|
|-
|
| 5
| FIFO overflow
|-
|
| 6
|
|-
|
| 7
|

|-
| 0x02
|
| '''Channel select low'''. Each 1 bit in this byte enables one of the channels 0-7 for acquisition.
|-
| 0x03
|
| '''Channel select high'''. Each 1 bit in this byte enables one of the channels 8-15 for acquisition.
|-
| 0x04
|
| '''Sampling rate divisor'''. Sample rate is the base clock divided by N+1, where N is the value in this register.
|-
| 0x05
|
| '''LED brightness'''. 0 = min (off), 0xff = max, 0x19 = dimmed.
|-
| 0x06
|
| ?
|-
| 0x07
|
| ?
|-
| 0x08
|
| ? (Read on acquisition stop.)
|-
| 0x09
|
| ? (Read on acquisition stop.)
|-
| 0x0a
|
|
|-
|
| 0
| Sampling base clock select: 0 = 100MHz, 1 = 160MHz
|-
|
| 1
|
|-
|
| 2
|
|-
|
| 3
|
|-
|
| 4
|
|-
|
| 5
|
|-
|
| 6
|
|-
|
| 7
|

|-
| 0x0c
|
| ?
|}

== EEPROM layout ==

The Saleae Logic16 has a 256-byte I2C EEPROM with the following layout:

c0 a9 21 01 10 00 00 00 aa bb cc dd ee ff gg hh
xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Description:

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Bytes
!Description
|-
| style="background-color: orange" | 0
| '''0xc0''': FX2 "c0 load" mode, i.e. VID/PID/DID are loaded from EEPROM (but not firmware).
|-
| style="background-color: lime" | 1-2
| '''0x21a9''': USB vendor ID (VID).
|-
| style="background-color: green" | 3-4
| '''0x1001''': USB product ID (PID).
|-
| style="background-color: lightgreen" | 5-6
| '''0x0000''': USB device ID (DID).
|-
| style="background-color: brown" | 7
| '''0x00''': FX2 configuration byte (see FX2 TRM for details).
|-
| style="background-color: yellow" | 8-15
| A unique device identifier / serial number for this Logic16 (8 bytes).
|-
| style="background-color: cyan" | 16-31
| "Magic" values that are different for each Logic16 device (16 bytes).
|}

Saleae Logic16/Firmware

2014-08-17T12:15:13Z

Marcus Comstedt: /* FPGA variables */ Document FIFO overflow bit

The following information is related to the vendor firmware included with the version 1.1.15 of the vendor application "Logic".

== Interrupt handlers ==

The following interrupt handlers are installed. If the address is absent, it means the handler just returns (RETI) without performing any action.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Handler
!Address
|-
| RESET
| 0x0000
|-
| TF2
| 0x0e65
|-
| RESUME
| 0x002e
|-
| SUDAV
| 0x0ae8
|-
| SOF
| 0x13d2
|-
| SUTOK
| 0x13bf
|-
| SUSPEND
| 0x13aa
|-
| USB_RESET
| 0x130b
|-
| HISPEED
| 0x12df
|-
| EP0ACK
|
|-
| EP0_IN
|
|-
| EP0_OUT
|
|-
| EP1_IN
|
|-
| EP1_OUT
| 0x115d
|-
| EP2
| 0x11a2
|-
| EP4
|
|-
| EP6
|
|-
| EP8
|
|-
| IBN
|
|-
| EP0PING
|
|-
| EP1PING
|
|-
| EP2PING
|
|-
| EP4PING
|
|-
| EP6PING
|
|-
| EP8PING
|
|-
| ERRLIMIT
|
|-
| EP2ISOERR
|
|-
| EP4ISOERRF
|
|-
| EP6ISOERR
|
|-
| EP8ISOERRF
|
|-
| EP2PF
|
|-
| EP4PF
|
|-
| EP6PF
|
|-
| EP8PF
|
|-
| EP2EF
|
|-
| EP4EF
|
|-
| EP6EF
|
|-
| EP8EF
|
|-
| EP2FF
| 0x11e7
|-
| EP4FF
|
|-
| EP6FF
|
|-
| EP8FF
|
|-
| GPIFDONE
|
|-
| GPIFWF
|
|}

=== Endpoint 1 OUT (EP1_OUT) handler ===

After decrypting the OUT packet, processing of the packet proceeds depending on the first byte of the packet, which selects the operation. After the operation, any resulting IN packet will be encrypted before submitting it to the host.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Byte
!Handler
!Operation
|-
| 1
| 0x14f
| Configure endpoints for quad-buffered bulk FIFO operation, and trigger a GPIF read on EP2.
|-
| 2
| 0x157
| Abort the GPIF.
|-
| 6
| 0x15f
| Write data to EEPROM with I²C address 1010000 (0x50) in single byte addressing mode. The second and third byte contain a fixed magic cookie of '''0x42 0x55'''. The fourth byte contains the single byte address. The fifth byte contains the number of bytes to write (1-58). The rest of the packet contains the data to write.
|-
| 7
| 0x1b3
| Read data from EEPROM with I²C address 1010000 (0x50) in single byte addressing mode. The second and third byte contain a fixed magic cookie of '''0x33 0x81'''. The fourth byte contains the single byte address. The fifth byte contains the number of bytes to read (1-64). The data will be available as an IN transfer.
|-
| 0x7a
| 0x309
| Upload the sine table for LED flashing. The second byte contains the offset to start writing at, and the third byte the number of bytes to write. A maximum of 61 bytes can be uploaded per packet, so two packets are needed to write the entire table.
|-
| 0x7b
| 0x346
| Enable or disable LED flashing. The second byte of the packet is a bool indicating if LED flashing should be enabled. The following bytes are only used if LED flashing is enabled, but are always transmitted. If flashing is enabled, the LED brighness will periodically be set from the sine table. Byte 3 and 4 of the packet are the Timer 2 reload value, in little endian format. Byte 5 is a software clock divisor. The pointer in the sine table will be advanced by one every '''(0x10000 - RELOAD) * (DIV + 1) / 4000000''' seconds. Byte 6 is a boolean indicating whether to repeat the waveform (1) or stop at the end of the first period (0).
|-
| 0x7c
| 0x282
| Re-renumerate; return control to the builtin bootloader.
|-
| 0x7d
| 0x2aa
| Abort the GPIF. The second byte of the packet is returned complemented in an IN transfer, as acknowledgement.
|-
| 0x7e
| 0x2cf
| Disable LED flashing, configure the GPIF, and prepare the FPGA for bitstream upload by pulsing '''PROG_B''' and then waiting for '''INIT_B'''.
|-
| 0x7f
| 0x2e4
| Disable LED flashing, transmit N (1-62) bytes of bitstream on the FPGA '''DIN''' pin, clocked by '''CCLK'''. The second byte of the packet encodes N.
|-
| 0x80
| 0x205
| Transmit N (1-31) 16-bit words to the FPGA. The second byte of the packet encodes N. Data is sent on '''PA6''', MSB-first, with rising edges of '''PA5''' to clock the bits out. During each word transfer, '''PA4''' is held low. The most significant bit (b15) of each word must be 0.
|-
| 0x81
| 0x23b
| Perform N (1-31) write-read transactions to the FPGA. The second byte of the packet encodes N. Each transaction consists of 8 bits (from the out packet) being transmitted on '''PA6''', like for the 0x80 operation above, and then 8 bits being received on '''PA7'''. N bytes will be available for an IN transfer afterwards. The most significant bit (b7) of each byte to send must be 0, but is actually transmitted as a 1 (to indicate read operation). '''PA7''' is polled immediately after the falling edge of '''PA5'''. '''PA4''' is held low during each write-read transaction.
|-
| 0x82
| 0x3a3
| Read the REVID register. 16 bits of '''REVID''' data will be available for an IN transfer.
|-
| others
| 0x3c7
| Do nothing
|}

==== Command 0x7e waveform ====

[[File:Logic16 FW Command 0x7e Waveform.svg]]

==== Command 0x7f waveform ====

[[File:Logic16 FW Command 0x7f Waveform.svg]]

==== Command 0x80 waveform ====

[[File:Logic16 FW Command 0x80 Waveform.svg]]

==== Command 0x81 waveform ====

[[File:Logic16 FW Command 0x81 Waveform.svg]]

== XDATA variables ==

The following variables are stored in the 8K "external" code/data memory, after the firmware code.

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!rowspan="2"|Address
!colspan="2"|Init data in FW
!rowspan="2"|Contents
|-
!Address
!Value
|-
| 0x1f00-0x1f7f
| 0x8d6-0x955
|
| WAVEDATA
|-
| 0x1f80
| 0x981
| 0xe0
| GPIFREADYCFG
|-
| 0x1f81
| 0x982
| 0x10
| GPIFCTLCFG
|-
| 0x1f82
| 0x983
| 0x00
| GPIFIDLECS
|-
| 0x1f83
| 0x984
| 0x05
| GPIFIDLECTL
|-
| 0x1f84
| 0x985
| 0xee
| ?
|-
| 0x1f85
| 0x986
| 0x50
| GPIFWFSELECT
|-
| 0x1f86
| 0x987
| 0x00
| GPIFREADYSTAT
|-
| 0x1f87
| 0x95a
| 0x00
| FLOWSTATE
|-
| 0x1f88
| 0x95b
| 0x00
| FLOWLOGIC
|-
| 0x1f89
| 0x95c
| 0x00
| FLOWEQ0CTL
|-
| 0x1f8a
| 0x95d
| 0x00
| FLOWEQ1CTL
|-
| 0x1f8b
| 0x95e
| 0x00
| FLOWHOLDOFF
|-
| 0x1f8c
| 0x95f
| 0x00
| FLOWSTB
|-
| 0x1f8d
| 0x960
| 0x00
| FLOWSTBEDGE
|-
| 0x1f8e
| 0x961
| 0x00
| FLOWSTBHPERIOD
|-
| 0x1f8f-0x1faa
| 0x962-0x97d
| 0x00
| ?
|-
| 0x1fab-0x1fea
|
|
| 64 byte sine table for LED flashing
|}

=== WAVEDATA ===

The following data is loaded into WAVEDATA on bootup, and whenever operation 0x7e is performed:

==== Waveform descriptor 0 ====

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!State
!Length/Branch
!Opcode
!Output
!Logic
!Operation
!NEXT
!DATA
!CTL2
!CTL1
!CTL0
|-
| 0
| 0x81
| 0x01
| 0x05
| 0x70
| if FF or RDY0 then 0 (ReExec) else 1
| 0
| 0
| 1
| 0
| 1
|-
| 1
| 0xB8
| 0x07
| 0x04
| 0x2D
| if TC expired then 7 else 0
| 1
| 1
| 1
| 0
| 0
|-
| 2
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 3
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 4
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 5
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|-
| 6
| 0x01
| 0x02
| 0x04
| 0x00
| Delay 1
| 0
| 1
| 1
| 0
| 0
|}

==== Waveform descriptor 1-3 ====

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!State
!Length/Branch
!Opcode
!Output
!Logic
!Operation
!NEXT
!DATA
!CTL2
!CTL1
!CTL0
|-
| 0-6
| 0x01
| 0x00
| 0x05
| 0x00
| Delay 1
| 0
| 0
| 1
| 0
| 1
|}

== FPGA variables ==

The following variables can be read and written by the host using operations 0x81 and 0x80:

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
! Address
! Contents
|-
| 0x00
| '''FPGA bitstream version''' (currently 0x10).
|-
| 0x01
| '''Status and control'''. Bit 0 = acquisition running. Bit 1 = update acquisition parameters(?). Bit 3 = ?. Bit 5 = FIFO overflow. Bit 6 = ?.
|-
| 0x02
| '''Channel select low'''. Each 1 bit in this byte enables one of the channels 0-7 for acquisition.
|-
| 0x03
| '''Channel select high'''. Each 1 bit in this byte enables one of the channels 8-15 for acquisition.
|-
| 0x04
| '''Sampling rate divisor'''. Sample rate is the base clock divided by N+1, where N is the value in this register.
|-
| 0x05
| '''LED brightness'''. 0 = min (off), 0xff = max, 0x19 = dimmed.
|-
| 0x06
| ?
|-
| 0x07
| ?
|-
| 0x08
| ? (Read on acquisition stop.)
|-
| 0x09
| ? (Read on acquisition stop.)
|-
| 0x0a
| Bit 7 = ?. Bit 6 = ?. Bit 0 = Sampling base clock select: 0 = 100MHz, 1 = 160MHz.
|-
| 0x0c
| ?
|}

== EEPROM layout ==

The Saleae Logic16 has a 256-byte I2C EEPROM with the following layout:

c0 a9 21 01 10 00 00 00 aa bb cc dd ee ff gg hh
xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Description:

{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
!Bytes
!Description
|-
| style="background-color: orange" | 0
| '''0xc0''': FX2 "c0 load" mode, i.e. VID/PID/DID are loaded from EEPROM (but not firmware).
|-
| style="background-color: lime" | 1-2
| '''0x21a9''': USB vendor ID (VID).
|-
| style="background-color: green" | 3-4
| '''0x1001''': USB product ID (PID).
|-
| style="background-color: lightgreen" | 5-6
| '''0x0000''': USB device ID (DID).
|-
| style="background-color: brown" | 7
| '''0x00''': FX2 configuration byte (see FX2 TRM for details).
|-
| style="background-color: yellow" | 8-15
| A unique device identifier / serial number for this Logic16 (8 bytes).
|-
| style="background-color: cyan" | 16-31
| "Magic" values that are different for each Logic16 device (16 bytes).
|}

Saleae Logic16/Firmware

2013-08-05T12:28:37Z

Marcus Comstedt: /* FPGA variables */

Saleae Logic16/Firmware

2013-07-31T21:34:13Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operations 2 and 6.

Saleae Logic16/Firmware

2013-07-31T20:46:21Z

Marcus Comstedt: /* FPGA variables */

Saleae Logic16/Firmware

2013-07-31T20:38:06Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operation 0x7

Saleae Logic16/Firmware

2013-07-31T20:03:38Z

Marcus Comstedt: /* XDATA variables */ Identify XDATA variables controlling FLOW registers

Saleae Logic16/Firmware

2013-07-31T19:56:15Z

Marcus Comstedt: /* XDATA variables */ Table at 0x1f87 is cleared to all zeroes

Saleae Logic16/Firmware

2013-07-31T19:38:47Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operations 0x7a and 0x7b

Saleae Logic16/Firmware

2013-07-31T17:58:30Z

Marcus Comstedt: /* FPGA variables */ Add LED brightness variable

Saleae Logic16/Firmware

2013-07-29T11:57:35Z

Marcus Comstedt: /* Waveform descriptor 1-3 */ Expand the other waveform descriptors too

Saleae Logic16/Firmware

2013-07-29T11:53:20Z

Marcus Comstedt: /* Waveform descriptor 0 */ Expand waveform descriptor 0

Saleae Logic16/Firmware

2013-07-29T11:24:48Z

Marcus Comstedt: /* WAVEDATA */ Oops, transposed the WAVEDATA tables...

Saleae Logic16/Firmware

2013-07-29T10:35:40Z

Marcus Comstedt: /* XDATA variables */ Added dumps of the waveform descriptors

Saleae Logic16/Firmware

2013-07-28T21:58:20Z

Marcus Comstedt: Added section on XDATA variables

File:Logic16 FW Command 0x7e Waveform.svg

2013-07-26T18:00:40Z

Marcus Comstedt: Marcus Comstedt uploaded a new version of "File:Logic16 FW Command 0x7e Waveform.svg": Hand tweaked the placement of the arrow heads, which got munged in the export from WaveDrom...

== Licensing ==
{{PD}}

Saleae Logic16/Firmware

2013-07-26T17:52:06Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Added waveforms for command 0x7e and 0x7f

File:Logic16 FW Command 0x7f Waveform.svg

2013-07-26T17:48:43Z

Marcus Comstedt:

== Licensing ==
{{PD}}

File:Logic16 FW Command 0x7e Waveform.svg

2013-07-26T17:47:47Z

Marcus Comstedt:

== Licensing ==
{{PD}}

Saleae Logic16/Firmware

2013-07-26T15:12:32Z

Marcus Comstedt: Added a section on FPGA config variables

Saleae Logic16

2013-07-26T15:04:26Z

Marcus Comstedt: /* Protocol */ Completed channel number and sampling frequency tables

{{Infobox logic analyzer
| image = [[File:Saleae Logic16.jpg|180px]]
| name = Saleae Logic16
| status = planned
| source_code_dir =
| channels = 2/4/8/16
| samplerate = 100/50/25/12.5MHz
| samplerate_state = —
| triggers = none (SW-only)
| voltages = -0.9V — 6V
| threshold = configurable: for 1.8V to 3.6V systems: VIH=1.4V, VIL=0.7V for 5V systems: VIH=3.6V, VIL=1.4V
| memory = none
| compression = yes
| website = [http://www.saleae.com/logic16/ saleae.com]
}}

The '''Saleae Logic16''' is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* '''FPGA''': [http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/spartan-3a.html Xilinx Spartan-3A XC3S200A], 200K gates ([http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf datasheeet])
* '''USB interface chip''': [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A-56PVXC (FX2LP)] ([http://www.cypress.com/?docID=34060 datasheet])
* '''Ultralow capacitance ESD protection''': 4x [http://www.st.com/web/catalog/sense_power/FM114/CL1137/SC1490/PF109008 ST DVIULC6-4SC6] ([http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00065974.pdf datasheet])
* '''I2C EEPROM''': Unknown. Marking: "B2TH".
* '''?''': 2x Unknown 5-pin IC. Markings: "189Z" and "189C".
* '''?''': 2x Unknown 3-pin IC. Markings: "72Y7".

== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
</gallery>

== Firmware ==

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

See [[Saleae Logic16/Firmware]] for more details on the vendor firmware.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. The transfers are "encrypted" using a simple series of additions and XORs. Two kinds of transfers are used; a 3 byte out transfer starting with 0x81 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x80. It's quite plausible that these provide raw read/write access to memory locations.

{| class="wikitable"
!colspan="2"|Channel number configuration
|-
|3 channels
|<tt>0x80 0x01 0x02 0x07 0x80 0x01 0x03 0x00</tt>
|-
|6 channels
|<tt>0x80 0x01 0x02 0x3f 0x80 0x01 0x03 0x00</tt>
|-
|9 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0x01</tt>
|-
|16 channels
|<tt>0x80 0x01 0x02 0xff 0x80 0x01 0x03 0xff</tt>
|}

{| class="wikitable"
!colspan="2"|Sampling frequency
|-
|500 kHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0xc7</tt>
|-
|1 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x63</tt>
|-
|2 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x31</tt>
|-
|4 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x18</tt>
|-
|5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x13</tt>
|-
|8 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x13</tt>
|-
|10 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x09</tt>
|-
|12.5 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x07</tt>
|-
|16 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x09</tt>
|-
|25 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x03</tt>
|-
|32 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x04</tt>
|-
|40 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x03</tt>
|-
|50 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x01</tt>
|-
|80 MHz
|<tt>0x80 0x01 0x0a 0x01 0x80 0x01 0x04 0x01</tt>
|-
|100 MHz
|<tt>0x80 0x01 0x0a 0x00 0x80 0x01 0x04 0x00</tt>
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Planned]]

Saleae Logic16/Firmware

2013-07-26T13:29:12Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operation 1.

Saleae Logic16/Firmware

2013-07-26T12:25:29Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operations 0x7c and 0x7d.

Saleae Logic16/Firmware

2013-07-25T21:35:39Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */

Saleae Logic16/Firmware

2013-07-25T21:32:26Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */

Saleae Logic16/Firmware

2013-07-25T21:31:41Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operations 0x7e and 0x7f

Saleae Logic16/Firmware

2013-07-25T21:25:26Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Added waveforms for command 0x80 and 0x81

File:Logic16 FW Command 0x81 Waveform.svg

2013-07-25T21:20:58Z

Marcus Comstedt:

== Licensing ==
{{PD}}

File:Logic16 FW Command 0x80 Waveform.svg

2013-07-25T21:05:25Z

Marcus Comstedt:

== Licensing ==
{{PD}}

Saleae Logic16/Firmware

2013-07-24T20:38:41Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Mention IN encryption

Saleae Logic16/Firmware

2013-07-24T20:37:43Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operation 0x82

Saleae Logic16/Firmware

2013-07-24T20:31:16Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operation 0x81

Saleae Logic16/Firmware

2013-07-24T20:06:43Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */

Saleae Logic16/Firmware

2013-07-24T20:04:48Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */

Saleae Logic16/Firmware

2013-07-24T20:03:16Z

Marcus Comstedt: /* Endpoint 1 OUT (EP1_OUT) handler */ Explain operation 0x80

Saleae Logic16/Firmware

2013-07-24T18:01:34Z

Marcus Comstedt: Added dispatch table for EP1_OUT handler

Saleae Logic16

2013-07-24T16:07:36Z

Marcus Comstedt: /* Protocol */ Decrypted the configuration transfers

Saleae Logic16

2013-07-23T09:54:03Z

Marcus Comstedt:

[[File:Saleae Logic16.jpg|thumb|right|Saleae Logic16, front]]

The [http://www.saleae.com/logic16/ Saleae Logic16] is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf Xilinx XC3S200A] 200K gate FPGA
* Cypress CY7C68013A-56PVXC (FX2LP) USB interface chip

== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
</gallery>

== Firmware ==

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

See [[Saleae Logic16/Firmware]] for more details on the vendor firmware.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. Two kinds of transfers are used; a 3 byte out transfer starting with 0x55 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x5a. It's quite plausible that these provide raw read/write access to memory locations.

{| class="wikitable"
!colspan="2"|Channel number configuration
|-
|3 channels
|0x5a 0x32 0xf4 0x38 0x5a 0x32 0xef 0x1b
|-
|6 channels
|0x5a 0x32 0xf4 0xc0 0x5a 0x32 0xef 0x1b
|-
|9 channels
|0x5a 0x32 0xf4 0x80 0x5a 0x32 0xef 0xc8
|}

{| class="wikitable"
!colspan="2"|Sampling frequency
|-
|500 kHz
|0x5a 0x32 0x4c 0x61 0x5a 0x32 0x82 0xb0
|-
|8 MHz
|0x5a 0x32 0x4c 0x5e 0x5a 0x32 0x82 0x0c
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Planned]]

Saleae Logic16/Firmware

2013-07-23T09:48:42Z

Marcus Comstedt: Created page with "The following information is related to the vendor firmware included with the version 1.1.15 of the vendor application "Logic". == Interrupt handlers == The following interrup..."

Saleae Logic16

2013-07-22T14:24:53Z

Marcus Comstedt: Some notes on configuration transfers on EP1

[[File:Saleae Logic16.jpg|thumb|right|Saleae Logic16, front]]

The [http://www.saleae.com/logic16/ Saleae Logic16] is a USB-based, 16-channel logic analyzer with 100/50/25/12.5MHz sampling rate (at 2/4/8/16 enabled channels).

The case requires a '''Torx T5''' screwdriver to open.

See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device.

See [[Saleae Logic]] for the predecessor product of the Saleae Logic16.

== Hardware ==

* [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf Xilinx XC3S200A] 200K gate FPGA
* Cypress CY7C68013A-56PVXC (FX2LP) USB interface chip

== Photos ==

<gallery>
File:Saleae Logic16.jpg|Device, front
File:Saleae Logic16 bottom.jpg|Device, bottom
File:Saleae Logic16 PCB top.jpg|PCB, top
File:Saleae Logic16 PCB bottom.jpg|PCB, bottom
</gallery>

== Firmware ==

The firmware for the FX2LP is embedded in the vendor application as a set of Intel HEX lines. Each line is uploaded individually with a separate control transfer. The firmware currently occupies the address range [0x0000-0x145d], but is uploaded out of order. TODO: Make a tool to extract the firmware from the application binary.

== Protocol ==

'''Sample format''':

The samples (as received via USB) for the enabled probes (3, 6, 9, or 16) are organized as follows:

'''0xLL 0xLL 0xMM 0xMM 0xNN 0xNN 0xPP 0xPP 0xQQ 0xQQ 0xRR 0xRR ...'''

In the above example, 3 probes are enabled. For each probe there are 2 bytes / 16 bits (e.g. 0xLL 0xLL for probe 0), then the next probe's data is received (0xMM 0xMM for probe 1), then 0xNN 0xNN for probe 2. When 2 bytes have been received for all enabled probes, the process restarts with probe 0 again.

The 16 bits of data per probe seem to contain the pin state of the respective probe (1: high, 0: low) at 16 different sampling points/times (which ones depends on the samplerate).

'''Configuration''':

Endpoint 1 is used for configuration of the analyzer. Two kinds of transfers are used; a 3 byte out transfer starting with 0x55 followed by a 1 byte in transfer, and a 4 byte out transfer starting with 0x5a. It's quite plausible that these provide raw read/write access to memory locations.

{| class="wikitable"
!colspan="2"|Channel number configuration
|-
|3 channels
|0x5a 0x32 0xf4 0x38 0x5a 0x32 0xef 0x1b
|-
|6 channels
|0x5a 0x32 0xf4 0xc0 0x5a 0x32 0xef 0x1b
|-
|9 channels
|0x5a 0x32 0xf4 0x80 0x5a 0x32 0xef 0xc8
|}

{| class="wikitable"
!colspan="2"|Sampling frequency
|-
|500 kHz
|0x5a 0x32 0x4c 0x61 0x5a 0x32 0x82 0xb0
|-
|8 MHz
|0x5a 0x32 0x4c 0x5e 0x5a 0x32 0x82 0x0c
|}

== Resources ==

* [http://downloads.saleae.com/Logic+Guide.pdf Manual]
* [http://www.saleae.com/downloads Vendor software]
* [http://community.saleae.com/ SDKs]

[[Category:Device]]
[[Category:Logic analyzer]]
[[Category:Planned]]

Saleae Logic16

2013-07-21T10:51:53Z

Marcus Comstedt: Some notes on the firmware