uart: Add a test-case with intentional parity errors.

[sigrok-test.git] / decoder / test / uart / test.conf

diff --git a/decoder/test/uart/test.conf b/decoder/test/uart/test.conf
index 21f1fac283a8143c4851c5d5b5c3a555cf839e75..383a8911bb5ba87de00b92f9e41b303c7d40c027 100644 (file)
--- a/decoder/test/uart/test.conf
+++ b/decoder/test/uart/test.conf
@@ -16,6 +16,14 @@ test hello_world_7o1_115200
        output uart python match hello_world_7o1_115200.python
        output uart binary class tx match hello_world_7o1_115200.bin_tx
 
+# Intentionally cause parity errors.
+test hello_world_7o1_115200_parity_err
+       protocol-decoder uart channel tx=0 option baudrate=115200 option parity_type=even option num_data_bits=7 option format=ascii
+       input uart/hello_world/7o1/hello_world_7o1_115200.sr
+       output uart annotation match hello_world_7o1_115200_parity_err.output
+       output uart python match hello_world_7o1_115200_parity_err.python
+       output uart binary class tx match hello_world_7o1_115200_parity_err.bin_tx
+
 test hello_world_7e1_115200
        protocol-decoder uart channel tx=0 option baudrate=115200 option parity_type=even option num_data_bits=7 option format=ascii
        input uart/hello_world/7e1/hello_world_7e1_115200.sr