X-Git-Url: http://sigrok.org/gitweb/?p=pulseview.git;a=blobdiff_plain;f=test%2Fdata%2Flogicsnapshot.cpp;fp=test%2Fdata%2Flogicsnapshot.cpp;h=951e3845b1d5651d2c739bbf88d35261965b9477;hp=1c536791b7a3f746a9ae621cc39c62553b21fae7;hb=6092d96f5d3c4c870b6e476237a105b5f037df70;hpb=83259518cae8c8e51ebbe1edba742ac8733ca76a

diff --git a/test/data/logicsnapshot.cpp b/test/data/logicsnapshot.cpp
index 1c536791..951e3845 100644
--- a/test/data/logicsnapshot.cpp
+++ b/test/data/logicsnapshot.cpp
@@ -471,5 +471,42 @@ BOOST_AUTO_TEST_CASE(LisaMUsbHid)
 	BOOST_CHECK_EQUAL(edges[edges.size() - 2].second, false);
 }
 
+/*
+ * This test checks the rendering of wide data (more than 8 probes)
+ * Probe signals are either all-high, or all-low, but are interleaved such that
+ * they would toggle during every sample if treated like 8 probes.
+ * The packet contains a large number of samples, so the mipmap generation kicks
+ * in.
+ *
+ * The signals should not toggle (have exactly two edges: the start and end)
+ */
+BOOST_AUTO_TEST_CASE(WideData)
+{
+	const int Length = 512<<10;
+	uint16_t *data = new uint16_t[Length];
+
+	sr_datafeed_logic logic;
+	logic.unitsize = sizeof(data[0]);
+	logic.length = Length * sizeof(data[0]);
+	logic.data = data;
+
+	for(int i = 0; i < Length; i++)
+		data[i] = 0x0FF0;
+
+	LogicSnapshot s(logic);
+
+	vector<LogicSnapshot::EdgePair> edges;
+
+	edges.clear();
+	s.get_subsampled_edges(edges, 0, Length-1, 1, 0);
+	BOOST_CHECK_EQUAL(edges.size(), 2);
+
+	edges.clear();
+	s.get_subsampled_edges(edges, 0, Length-1, 1, 8);
+	BOOST_CHECK_EQUAL(edges.size(), 2);
+
+	// Cleanup
+	delete [] data;
+}
 
 BOOST_AUTO_TEST_SUITE_END()