X-Git-Url: http://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Ftlc5620%2Fpd.py;h=f8c90d96b52c05c818bdd89d949edf4e75174ea9;hp=3fccd479ba479a74eec680683419a948b2f9f426;hb=HEAD;hpb=af495297728b449832a4f780d1f59c1cea5c295d

diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 3fccd47..8ff30d7 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -14,11 +14,13 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'CLK DATA LOAD LDAC')
 
 dacs = {
     0: 'DACA',
@@ -35,7 +37,8 @@ class Decoder(srd.Decoder):
     desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['tlc5620']
+    outputs = []
+    tags = ['IC', 'Analog/digital']
     channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
         {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
@@ -72,6 +75,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.bits = []
         self.ss_dac_first = None
         self.ss_dac = self.es_dac = 0
@@ -194,7 +200,7 @@ class Decoder(srd.Decoder):
             #   a) Falling edge on CLK, and/or
             #   b) Falling edge on LOAD, and/or
             #   b) Falling edge on LDAC
-            pins = self.wait([{0: 'f'}, {2: 'f'}, {3: 'f'}])
+            pins = self.wait([{Pin.CLK: 'f'}, {Pin.LOAD: 'f'}, {Pin.LDAC: 'f'}])
             self.ldac = pins[3]
 
             # Handle those conditions (one or more) that matched this time.