X-Git-Url: http://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fsda2506%2Fpd.py;fp=decoders%2Fsda2506%2Fpd.py;h=6df57554f69f0176facddd0d06682616bfcdfef7;hp=5b071d88d57d3a3cadaa6a4d4bb949403f396373;hb=c81a365e0e81482c601371f9be8a47a048a0aae0;hpb=32eae3386b49b6d03c6f424517d21b0c64ce9b35

diff --git a/decoders/sda2506/pd.py b/decoders/sda2506/pd.py
index 5b071d8..6df5755 100644
--- a/decoders/sda2506/pd.py
+++ b/decoders/sda2506/pd.py
@@ -19,6 +19,9 @@
 
 import re
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'CLK DATA CE')
 
 ann_cmdbit, ann_databit, ann_cmd, ann_data, ann_warning = range(5)
 
@@ -88,8 +91,8 @@ class Decoder(srd.Decoder):
 
     def decode(self):
         while True:
-            # Wait for CLK edge or CE edge.
-            clk, d, ce = self.wait([{0: 'e'}, {2: 'e'}])
+            # Wait for CLK edge or CE# edge.
+            clk, d, ce = self.wait([{Pin.CLK: 'e'}, {Pin.CE: 'e'}])
 
             if self.matched[0] and ce == 1 and clk == 1:
                 # Rising clk edge and command mode.