X-Git-Url: http://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Flpc%2Fpd.py;h=5e25db4779ba886070fecd752ecf848926eec966;hp=ef782e0cdc91f3cf86fdd6ada31c680d03c35c97;hb=HEAD;hpb=780770f1295b7fdeb4481eb42623bad5da1e19a7 diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py index ef782e0..2a88e30 100644 --- a/decoders/lpc/pd.py +++ b/decoders/lpc/pd.py @@ -14,8 +14,7 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd @@ -96,23 +95,24 @@ fields = { } class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'lpc' name = 'LPC' - longname = 'Low-Pin-Count' + longname = 'Low Pin Count' desc = 'Protocol for low-bandwidth devices on PC mainboards.' license = 'gplv2+' inputs = ['logic'] - outputs = ['lpc'] - probes = [ + outputs = [] + tags = ['PC'] + channels = ( {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'}, {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'}, {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'}, {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'}, {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'}, {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'}, - ] - optional_probes = [ + ) + optional_channels = ( {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'}, {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'}, {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'}, @@ -120,27 +120,28 @@ class Decoder(srd.Decoder): {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'}, {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'}, {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'}, - ] - annotations = [ - ['warnings', 'Warnings'], - ['start', 'Start'], - ['cycle-type', 'Cycle-type/direction'], - ['addr', 'Address'], - ['tar1', 'Turn-around cycle 1'], - ['sync', 'Sync'], - ['data', 'Data'], - ['tar2', 'Turn-around cycle 2'], - ] + ) + annotations = ( + ('warning', 'Warning'), + ('start', 'Start'), + ('cycle-type', 'Cycle-type/direction'), + ('addr', 'Address'), + ('tar1', 'Turn-around cycle 1'), + ('sync', 'Sync'), + ('data', 'Data'), + ('tar2', 'Turn-around cycle 2'), + ) annotation_rows = ( - ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)), + ('data-vals', 'Data', (1, 2, 3, 4, 5, 6, 7)), ('warnings', 'Warnings', (0,)), ) - def __init__(self, **kwargs): + def __init__(self): + self.reset() + + def reset(self): self.state = 'IDLE' self.oldlclk = -1 - self.samplenum = 0 - self.clocknum = 0 self.lad = -1 self.addr = 0 self.cur_nibble = 0 @@ -152,7 +153,6 @@ class Decoder(srd.Decoder): self.ss_block = self.es_block = None def start(self): - # self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) def putb(self, data): @@ -185,10 +185,10 @@ class Decoder(srd.Decoder): def handle_get_ct_dr(self, lad, lad_bits): # LAD[3:0]: Cycle type / direction field (1 clock cycle). - self.cycle_type = fields['CT_DR'][lad] + self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown') # TODO: Warning/error on invalid cycle types. - if self.cycle_type == 'Reserved': + if 'Reserved' in self.cycle_type: self.putb([0, ['Invalid cycle type (%s)' % lad_bits]]) self.es_block = self.samplenum @@ -254,10 +254,10 @@ class Decoder(srd.Decoder): # LAD[3:0]: SYNC field (1-n clock cycles). self.sync_val = lad_bits - self.cycle_type = fields['SYNC'][lad] + self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown') # TODO: Warnings if reserved value are seen? - if self.cycle_type == 'Reserved': + if 'Reserved' in self.cycle_type: self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \ (self.synccount, self.sync_val)]]) @@ -314,12 +314,10 @@ class Decoder(srd.Decoder): self.tarcount = 0 self.state = 'IDLE' - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: - - # If none of the pins changed, there's nothing to do. - if self.oldpins == pins: - continue + def decode(self): + conditions = [{i: 'e'} for i in range(6)] + while True: + pins = self.wait(conditions) # Store current pin values for the next round. self.oldpins = pins @@ -338,7 +336,7 @@ class Decoder(srd.Decoder): # Most (but not all) states need this. if self.state != 'IDLE': lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0 - lad_bits = bin(lad)[2:].zfill(4) + lad_bits = '{:04b}'.format(lad) # self.putb([0, ['LAD: %s' % lad_bits]]) # TODO: Only memory read/write is currently supported/tested. @@ -347,11 +345,10 @@ class Decoder(srd.Decoder): if self.state == 'IDLE': # A valid LPC cycle starts with LFRAME# being asserted (low). if lframe != 0: - continue + continue self.ss_block = self.samplenum self.state = 'GET START' self.lad = -1 - # self.clocknum = 0 elif self.state == 'GET START': self.handle_get_start(lad, lad_bits, lframe) elif self.state == 'GET CT/DR': @@ -366,6 +363,3 @@ class Decoder(srd.Decoder): self.handle_get_data(lad, lad_bits) elif self.state == 'GET TAR2': self.handle_get_tar2(lad, lad_bits) - else: - raise Exception('Invalid state: %s' % self.state) -