X-Git-Url: http://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Flpc%2Fpd.py;h=5e25db4779ba886070fecd752ecf848926eec966;hp=7242208829b95109079b1699788d3a3e7f051b9d;hb=HEAD;hpb=10aeb8ea8b183394cebc0033f048f49f4262b57d diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py index 7242208..2a88e30 100644 --- a/decoders/lpc/pd.py +++ b/decoders/lpc/pd.py @@ -98,11 +98,12 @@ class Decoder(srd.Decoder): api_version = 3 id = 'lpc' name = 'LPC' - longname = 'Low-Pin-Count' + longname = 'Low Pin Count' desc = 'Protocol for low-bandwidth devices on PC mainboards.' license = 'gplv2+' inputs = ['logic'] - outputs = ['lpc'] + outputs = [] + tags = ['PC'] channels = ( {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'}, {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'}, @@ -121,7 +122,7 @@ class Decoder(srd.Decoder): {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'}, ) annotations = ( - ('warnings', 'Warnings'), + ('warning', 'Warning'), ('start', 'Start'), ('cycle-type', 'Cycle-type/direction'), ('addr', 'Address'), @@ -131,7 +132,7 @@ class Decoder(srd.Decoder): ('tar2', 'Turn-around cycle 2'), ) annotation_rows = ( - ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)), + ('data-vals', 'Data', (1, 2, 3, 4, 5, 6, 7)), ('warnings', 'Warnings', (0,)), ) @@ -141,7 +142,6 @@ class Decoder(srd.Decoder): def reset(self): self.state = 'IDLE' self.oldlclk = -1 - self.samplenum = 0 self.lad = -1 self.addr = 0 self.cur_nibble = 0 @@ -315,13 +315,9 @@ class Decoder(srd.Decoder): self.state = 'IDLE' def decode(self): + conditions = [{i: 'e'} for i in range(6)] while True: - # TODO: Come up with more appropriate self.wait() conditions. - pins = self.wait() - - # If none of the pins changed, there's nothing to do. - if self.oldpins == pins: - continue + pins = self.wait(conditions) # Store current pin values for the next round. self.oldpins = pins @@ -340,7 +336,7 @@ class Decoder(srd.Decoder): # Most (but not all) states need this. if self.state != 'IDLE': lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0 - lad_bits = bin(lad)[2:].zfill(4) + lad_bits = '{:04b}'.format(lad) # self.putb([0, ['LAD: %s' % lad_bits]]) # TODO: Only memory read/write is currently supported/tested.