pca9571/tca6408a: Rework logic output

[libsigrokdecode.git] / decoders / tca6408a / pd.py

diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py
index fdfebeddb23d92a26b31a98248993c4b7a405951..01c4e6d9bc764acd5db50458b1058d4b3b6236f3 100644 (file)
--- a/decoders/tca6408a/pd.py
+++ b/decoders/tca6408a/pd.py
@@ -56,7 +56,11 @@ class Decoder(srd.Decoder):
     def reset(self):
         self.state = 'IDLE'
         self.chip = -1
-        self.ss_logic = -1
+
+        self.logic_es = 1
+        self.logic_data = []
+        for i in range(NUM_OUTPUT_CHANNELS):
+            self.logic_data.append(bytes([1]))
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
@@ -65,8 +69,11 @@ class Decoder(srd.Decoder):
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
-    def putl(self, data):
-        self.put(self.ss_logic, self.ss_logic, self.out_logic, data)
+    def put_logic_states(self):
+        if (self.es > self.logic_es):
+            for i in range(NUM_OUTPUT_CHANNELS):
+                self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]])
+            self.logic_es = self.es
 
     def handle_reg_0x00(self, b):
         self.putx([1, ['State of inputs: %02X' % b]])
@@ -74,10 +81,9 @@ class Decoder(srd.Decoder):
 
     def handle_reg_0x01(self, b):
         self.putx([1, ['Outputs set: %02X' % b]])
-        self.ss_logic = self.ss
         for i in range(NUM_OUTPUT_CHANNELS):
             bit = (b & (1 << i)) != 0
-            self.putl([i, bytes([bit])])
+            self.logic_data[i] = bytes([bit])
 
     def handle_reg_0x02(self, b):
         self.putx([1, ['Polarity inverted: %02X' % b]])
@@ -107,6 +113,8 @@ class Decoder(srd.Decoder):
         # Store the start/end samples of this I²C packet.
         self.ss, self.es = ss, es
 
+        self.put_logic_states()
+
         # State machine.
         if self.state == 'IDLE':
             # Wait for an I²C START condition.