From: Uwe Hermann <redacted>
Date: Fri, 10 Jan 2020 16:49:28 +0000 (+0100)
Subject: cjtag: Use SrdStrEnum for the state machine.
X-Git-Url: http://sigrok.org/gitweb/?a=commitdiff_plain;h=99ef7b313ea573437598ab2b45b9d2c0e28b61a5;hp=1d0234b76c62aeb0498fbaffa79ac1765b13984d;p=libsigrokdecode.git

cjtag: Use SrdStrEnum for the state machine.
---

diff --git a/decoders/cjtag/pd.py b/decoders/cjtag/pd.py
index 3fb636a..9d2f751 100644
--- a/decoders/cjtag/pd.py
+++ b/decoders/cjtag/pd.py
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the libsigrokdecode project.
 ##
-## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2020 Uwe Hermann <uwe@hermann-uwe.de>
 ## Copyright (C) 2019 Zhiyuan Wan <dv.xw@qq.com>
 ## Copyright (C) 2019 Kongou Hikari <hikari@iloli.bid>
 ##
@@ -20,6 +20,7 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import SrdStrEnum
 
 '''
 OUTPUT_PYTHON format:
@@ -44,16 +45,12 @@ of '1' and '0' characters (the right-most character is the LSB. Example:
 for each bit that is in the bitstring.
 '''
 
-jtag_states = [
-        # Intro "tree"
-        'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
-        # DR "tree"
-        'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
-        'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
-        # IR "tree"
-        'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
-        'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
-]
+s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \
+     SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \
+     SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR'
+St = SrdStrEnum.from_str('St', s)
+
+jtag_states = [s.value for s in St]
 
 cjtag_states = [
         'CJTAG-EC', 'CJTAG-SPARE', 'CJTAG-TPDEL', 'CJTAG-TPREV', 'CJTAG-TPST',
@@ -99,8 +96,8 @@ class Decoder(srd.Decoder):
         self.reset()
 
     def reset(self):
-        # self.state = 'TEST-LOGIC-RESET'
-        self.state = 'RUN-TEST/IDLE'
+        # self.state = St.TEST_LOGIC_RESET
+        self.state = St.RUN_TEST_IDLE
         self.cjtagstate = '4-WIRE'
         self.oldcjtagstate = None
         self.escape_edges = 0
@@ -170,46 +167,46 @@ class Decoder(srd.Decoder):
                 self.oscan1cycle = 1
                 # Because Nuclei cJTAG device asserts a reset during cJTAG
                 # online activating.
-                self.state = 'TEST-LOGIC-RESET'
+                self.state = St.TEST_LOGIC_RESET
             return
 
         # Intro "tree"
-        if self.state == 'TEST-LOGIC-RESET':
-            self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
-        elif self.state == 'RUN-TEST/IDLE':
-            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
+        if self.state == St.TEST_LOGIC_RESET:
+            self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE
+        elif self.state == St.RUN_TEST_IDLE:
+            self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE
 
         # DR "tree"
-        elif self.state == 'SELECT-DR-SCAN':
-            self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
-        elif self.state == 'CAPTURE-DR':
-            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
-        elif self.state == 'SHIFT-DR':
-            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
-        elif self.state == 'EXIT1-DR':
-            self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
-        elif self.state == 'PAUSE-DR':
-            self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
-        elif self.state == 'EXIT2-DR':
-            self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
-        elif self.state == 'UPDATE-DR':
-            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
+        elif self.state == St.SELECT_DR_SCAN:
+            self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR
+        elif self.state == St.CAPTURE_DR:
+            self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR
+        elif self.state == St.SHIFT_DR:
+            self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR
+        elif self.state == St.EXIT1_DR:
+            self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR
+        elif self.state == St.PAUSE_DR:
+            self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR
+        elif self.state == St.EXIT2_DR:
+            self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR
+        elif self.state == St.UPDATE_DR:
+            self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE
 
         # IR "tree"
-        elif self.state == 'SELECT-IR-SCAN':
-            self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
-        elif self.state == 'CAPTURE-IR':
-            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
-        elif self.state == 'SHIFT-IR':
-            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
-        elif self.state == 'EXIT1-IR':
-            self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
-        elif self.state == 'PAUSE-IR':
-            self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
-        elif self.state == 'EXIT2-IR':
-            self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
-        elif self.state == 'UPDATE-IR':
-            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
+        elif self.state == St.SELECT_IR_SCAN:
+            self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR
+        elif self.state == St.CAPTURE_IR:
+            self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR
+        elif self.state == St.SHIFT_IR:
+            self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR
+        elif self.state == St.EXIT1_IR:
+            self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR
+        elif self.state == St.PAUSE_IR:
+            self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR
+        elif self.state == St.EXIT2_IR:
+            self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR
+        elif self.state == St.UPDATE_IR:
+            self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE
 
     def handle_rising_tckc_edge(self, tdi, tdo, tck, tms):
 
@@ -224,8 +221,8 @@ class Decoder(srd.Decoder):
             # Output the saved item (from the last CLK edge to the current).
             self.es_item = self.samplenum
             # Output the old state (from last rising TCK edge to current one).
-            self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
-            self.putp(['NEW STATE', self.state])
+            self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]])
+            self.putp(['NEW STATE', self.state.value])
 
             self.putx([len(jtag_states) + cjtag_states.index(self.oldcjtagstate),
                       [self.oldcjtagstate]])
@@ -234,8 +231,8 @@ class Decoder(srd.Decoder):
         self.oldtms = tms
 
         # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values.
-        if self.oldstate.startswith('SHIFT-') or \
-           self.oldstate.startswith('EXIT1-'):
+        if self.oldstate.value.startswith('SHIFT-') or \
+           self.oldstate.value.startswith('EXIT1-'):
             if self.first_bit:
                 self.ss_bitstring = self.samplenum
                 self.first_bit = False
@@ -254,11 +251,11 @@ class Decoder(srd.Decoder):
             self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
 
         # Output all TDI/TDO bits if we just switched to UPDATE-*.
-        if self.state.startswith('UPDATE-'):
+        if self.state.value.startswith('UPDATE-'):
 
             self.es_bitstring = self.samplenum
 
-            t = self.state[-2:] + ' TDI'
+            t = self.state.value[-2:] + ' TDI'
             b = ''.join(map(str, self.bits_tdi[1:]))
             h = ' (0x%x' % int('0b0' + b, 2) + ')'
             s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
@@ -267,7 +264,7 @@ class Decoder(srd.Decoder):
             self.bits_tdi = []
             self.bits_samplenums_tdi = []
 
-            t = self.state[-2:] + ' TDO'
+            t = self.state.value[-2:] + ' TDO'
             b = ''.join(map(str, self.bits_tdo[1:]))
             h = ' (0x%x' % int('0b0' + b, 2) + ')'
             s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'