From: Diego F. Asanza <redacted>
Date: Thu, 31 Mar 2016 20:16:12 +0000 (+0200)
Subject: Set DSLogic in logic analyzer mode.
X-Git-Tag: libsigrok-0.5.0~524
X-Git-Url: http://sigrok.org/gitweb/?a=commitdiff_plain;h=62974b235a5c5aeaacad5d28a50aef39f528dccd;p=libsigrok.git

Set DSLogic in logic analyzer mode.

It was being initialized in DSO mode.

Signed-off-by: Diego F. Asanza <redacted>
---

diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index 2f0ffa32..d3cce4d0 100644
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -117,7 +117,7 @@ SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 	int ret;
 
 	devc = sdi->priv;
-	mode.flags = 0;
+	mode.flags = DS_START_FLAGS_MODE_LA;
 	mode.sample_delay_h = mode.sample_delay_l = 0;
 	if (devc->sample_wide)
 		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h
index 411e8331..0a83bbd8 100644
--- a/src/hardware/fx2lafw/dslogic.h
+++ b/src/hardware/fx2lafw/dslogic.h
@@ -32,6 +32,7 @@
 #define DS_START_FLAGS_STOP		(1 << 7)
 #define DS_START_FLAGS_CLK_48MHZ	(1 << 6)
 #define DS_START_FLAGS_SAMPLE_WIDE	(1 << 5)
+#define DS_START_FLAGS_MODE_LA		(1 << 4)
 
 enum dslogic_operation_modes {
 	DS_OP_NORMAL,