From: Piotr Esden-Tempski <redacted>
Date: Sat, 16 Sep 2017 04:08:04 +0000 (-0700)
Subject: Recreated original schematic + input protection.
X-Git-Url: http://sigrok.org/gitweb/?a=commitdiff_plain;ds=sidebyside;h=3339fa437775195588013681e54c41fa2888a288;p=fx2grok.git

Recreated original schematic + input protection.
---

diff --git a/hardware/fx2grok-flat/0.2/fx2grok-flat-cache.lib b/hardware/fx2grok-flat/0.2/fx2grok-flat-cache.lib
new file mode 100644
index 0000000..d4fe560
--- /dev/null
+++ b/hardware/fx2grok-flat/0.2/fx2grok-flat-cache.lib
@@ -0,0 +1,444 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# +3V3
+#
+DEF +3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# +5V
+#
+DEF +5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# CY7C68013A-56
+#
+DEF CY7C68013A-56 IC 0 40 Y Y 1 F N
+F0 "IC" 0 -1700 60 H V C CNN
+F1 "CY7C68013A-56" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -1100 1400 1000 -1300 0 1 0 N
+X RDY0/SLRD 1 -1400 1300 300 R 50 50 1 1 I
+X RDY1/SLWR 2 -1400 1200 300 R 50 50 1 1 I
+X AVCC 3 200 1700 300 D 50 50 1 1 W
+X XTALOUT 4 -1400 1000 300 R 50 50 1 1 O
+X XTALIN 5 -1400 900 300 R 50 50 1 1 I
+X AGND 6 200 -1500 300 U 50 50 1 1 W
+X AVCC 7 300 1700 300 D 50 50 1 1 W
+X DPLUS 8 -1400 700 300 R 50 50 1 1 B
+X DMINUS 9 -1400 600 300 R 50 50 1 1 B
+X AGND 10 300 -1500 300 U 50 50 1 1 W
+X PB2/FD2 20 1300 200 300 L 50 50 1 1 B
+X CTL1/FLAGB 30 -1400 -300 300 R 50 50 1 1 O
+X PA7/FLAGD/~SLCS 40 1300 600 300 L 50 50 1 1 B
+X PD5/FD13 50 1300 -1000 300 L 50 50 1 1 B
+X VCC 11 -500 1700 300 D 50 50 1 1 W
+X PB3/FD3 21 1300 100 300 L 50 50 1 1 B
+X CTL2/FLAGC 31 -1400 -400 300 R 50 50 1 1 O
+X GND 41 -200 -1500 300 U 50 50 1 1 W
+X PD6/FD14 51 1300 -1100 300 L 50 50 1 1 B
+X GND 12 -500 -1500 300 U 50 50 1 1 W
+X PB4/FD4 22 1300 0 300 L 50 50 1 1 B
+X VCC 32 -200 1700 300 D 50 50 1 1 W
+X ~RESET 42 -1400 -600 300 R 50 50 1 1 I I
+X PD7/FD15 52 1300 -1200 300 L 50 50 1 1 B
+X IFCLK 13 -1400 400 300 R 50 50 1 1 B C
+X PB5/FD5 23 1300 -100 300 L 50 50 1 1 B
+X PA0/~INT0 33 1300 1300 300 L 50 50 1 1 B
+X VCC 43 -100 1700 300 D 50 50 1 1 W
+X GND 53 -100 -1500 300 U 50 50 1 1 W
+X RESERVED 14 -1400 -1000 300 R 50 50 1 1 I
+X PB6/FD6 24 1300 -200 300 L 50 50 1 1 B
+X PA1/~INT1 34 1300 1200 300 L 50 50 1 1 B
+X WAKEUP 44 -1400 -800 300 R 50 50 1 1 I
+X CLKOUT 54 -1400 300 300 R 50 50 1 1 O C
+X SCL 15 -1400 100 300 R 50 50 1 1 O
+X PB7/FD7 25 1300 -300 300 L 50 50 1 1 B
+X PA2/SLOE 35 1300 1100 300 L 50 50 1 1 B
+X PD0/FD8 45 1300 -500 300 L 50 50 1 1 B
+X VCC 55 0 1700 300 D 50 50 1 1 W
+X SDA 16 -1400 0 300 R 50 50 1 1 B
+X GND 26 -400 -1500 300 U 50 50 1 1 W
+X PA3/WU2 36 1300 1000 300 L 50 50 1 1 B
+X PD1/FD9 46 1300 -600 300 L 50 50 1 1 B
+X GND 56 0 -1500 300 U 50 50 1 1 W
+X VCC 17 -400 1700 300 D 50 50 1 1 W
+X VCC 27 -300 1700 300 D 50 50 1 1 W
+X PA4/FIFOADR0 37 1300 900 300 L 50 50 1 1 B
+X PD2/FD10 47 1300 -700 300 L 50 50 1 1 B
+X PB0/FD0 18 1300 400 300 L 50 50 1 1 B
+X GND 28 -300 -1500 300 U 50 50 1 1 W
+X PA5/FIFOADR1 38 1300 800 300 L 50 50 1 1 B
+X PD3/FD11 48 1300 -800 300 L 50 50 1 1 B
+X PB1/FD1 19 1300 300 300 L 50 50 1 1 B
+X CTL0/FLAGA 29 -1400 -200 300 R 50 50 1 1 O
+X PA6/PKTEND 39 1300 700 300 L 50 50 1 1 B
+X PD4/FD12 49 1300 -900 300 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# Conn_02x05_Odd_Even
+#
+DEF Conn_02x05_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 300 50 H V C CNN
+F1 "Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*2x??x*mm*
+ Connector*:*2x???Pitch*
+ Pin_Header_Straight_2X*
+ Pin_Header_Angled_2X*
+ Socket_Strip_Straight_2X*
+ Socket_Strip_Angled_2X*
+$ENDFPLIST
+DRAW
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 250 150 -250 1 1 10 f
+S 150 -195 100 -205 1 1 6 N
+S 150 -95 100 -105 1 1 6 N
+S 150 5 100 -5 1 1 6 N
+S 150 105 100 95 1 1 6 N
+S 150 205 100 195 1 1 6 N
+X Pin_1 1 -200 200 150 R 50 50 1 1 P
+X Pin_2 2 300 200 150 L 50 50 1 1 P
+X Pin_3 3 -200 100 150 R 50 50 1 1 P
+X Pin_4 4 300 100 150 L 50 50 1 1 P
+X Pin_5 5 -200 0 150 R 50 50 1 1 P
+X Pin_6 6 300 0 150 L 50 50 1 1 P
+X Pin_7 7 -200 -100 150 R 50 50 1 1 P
+X Pin_8 8 300 -100 150 L 50 50 1 1 P
+X Pin_9 9 -200 -200 150 R 50 50 1 1 P
+X Pin_10 10 300 -200 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DSILC6-4
+#
+DEF DSILC6-4 U 0 40 Y Y 1 F N
+F0 "U" 0 -300 60 H V C CNN
+F1 "DSILC6-4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C -140 -50 5 0 1 0 N
+C -140 0 5 0 1 0 N
+C -140 50 5 0 1 0 N
+C -25 -50 5 0 1 0 N
+C -25 50 5 0 1 0 N
+C 25 -150 5 0 1 0 N
+C 25 150 5 0 1 0 N
+C 140 -50 5 0 1 0 N
+C 140 0 5 0 1 0 N
+C 140 50 5 0 1 0 N
+S -300 200 300 -200 0 1 0 N
+P 2 0 1 0 -300 -100 -25 -100 N
+P 2 0 1 0 -300 0 -30 0 N
+P 2 0 1 0 -300 100 -25 100 N
+P 2 0 1 0 -50 -180 -50 -120 N
+P 2 0 1 0 -50 -150 50 -150 N
+P 2 0 1 0 -50 -50 50 -50 N
+P 2 0 1 0 -50 -20 -50 -80 N
+P 2 0 1 0 -50 20 -50 80 N
+P 2 0 1 0 -50 50 50 50 N
+P 2 0 1 0 -50 120 -50 180 N
+P 2 0 1 0 -50 150 50 150 N
+P 2 0 1 0 -25 -50 -25 -100 N
+P 2 0 1 0 -25 50 -25 100 N
+P 2 0 1 0 30 0 300 0 N
+P 2 0 1 0 110 -180 110 -120 N
+P 2 0 1 0 110 -20 110 -80 N
+P 2 0 1 0 110 80 110 20 N
+P 2 0 1 0 110 120 110 180 N
+P 2 0 1 0 110 150 140 150 N
+P 2 0 1 0 140 150 140 50 N
+P 3 0 1 0 -140 -50 -140 -150 -115 -150 N
+P 3 0 1 0 -140 0 -140 -50 -110 -50 N
+P 3 0 1 0 -110 50 -140 50 -140 0 N
+P 3 0 1 0 -110 150 -140 150 -140 50 N
+P 3 0 1 0 110 -50 140 -50 140 0 N
+P 3 0 1 0 110 50 140 50 140 0 N
+P 3 0 1 0 140 -50 140 -150 110 -150 N
+P 3 0 1 0 300 -100 25 -100 25 -150 N
+P 3 0 1 0 300 100 25 100 25 150 N
+P 4 0 1 0 -110 -180 -50 -150 -110 -120 -110 -180 N
+P 4 0 1 0 -110 -20 -110 -80 -50 -50 -110 -20 N
+P 4 0 1 0 -110 20 -50 50 -110 80 -110 20 N
+P 4 0 1 0 -110 120 -50 150 -110 180 -110 120 N
+P 4 0 1 0 -30 30 -30 -30 30 0 -30 30 N
+P 4 0 1 0 20 -30 30 -20 30 20 40 30 N
+P 4 0 1 0 50 -180 110 -150 50 -120 50 -180 N
+P 4 0 1 0 50 -20 110 -50 50 -80 50 -20 N
+P 4 0 1 0 50 80 50 20 110 50 50 80 N
+P 4 0 1 0 50 120 110 150 50 180 50 120 N
+X IO1 1 -500 100 200 R 50 50 1 1 B
+X GND 2 -500 0 200 R 50 50 1 1 W
+X IO2 3 -500 -100 200 R 50 50 1 1 B
+X IO3 4 500 -100 200 L 50 50 1 1 B
+X VBUS 5 500 0 200 L 50 50 1 1 W
+X IO4 6 500 100 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# USBLC6-2
+#
+DEF USBLC6-2 U 0 40 Y Y 1 F N
+F0 "U" 0 -300 60 H V C CNN
+F1 "USBLC6-2" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C -140 0 5 0 1 0 N
+C 0 -100 5 0 1 0 N
+C 0 -50 5 0 1 0 N
+C 0 50 5 0 1 0 N
+C 0 100 5 0 1 0 N
+C 140 0 5 0 1 0 N
+S -300 200 300 -200 0 1 0 N
+P 2 0 1 0 -300 -100 300 -100 N
+P 2 0 1 0 -300 0 -30 0 N
+P 2 0 1 0 -300 100 300 100 N
+P 2 0 1 0 -50 -50 50 -50 N
+P 2 0 1 0 -50 -20 -50 -80 N
+P 2 0 1 0 -50 20 -50 80 N
+P 2 0 1 0 -50 50 50 50 N
+P 2 0 1 0 0 -50 0 -100 N
+P 2 0 1 0 0 50 0 100 N
+P 2 0 1 0 30 0 300 0 N
+P 2 0 1 0 110 -20 110 -80 N
+P 2 0 1 0 110 80 110 20 N
+P 3 0 1 0 -140 0 -140 -50 -110 -50 N
+P 3 0 1 0 -110 50 -140 50 -140 0 N
+P 3 0 1 0 110 -50 140 -50 140 0 N
+P 3 0 1 0 110 50 140 50 140 0 N
+P 4 0 1 0 -110 -20 -110 -80 -50 -50 -110 -20 N
+P 4 0 1 0 -110 20 -50 50 -110 80 -110 20 N
+P 4 0 1 0 -30 30 -30 -30 30 0 -30 30 N
+P 4 0 1 0 20 -30 30 -20 30 20 40 30 N
+P 4 0 1 0 50 -20 110 -50 50 -80 50 -20 N
+P 4 0 1 0 50 80 50 20 110 50 50 80 N
+X IO1 1 -500 100 200 R 50 50 1 1 B
+X GND 2 -500 0 200 R 50 50 1 1 W
+X IO2 3 -500 -100 200 R 50 50 1 1 B
+X IO2 4 500 -100 200 L 50 50 1 1 B
+X VBUS 5 500 0 200 L 50 50 1 1 W
+X IO1 6 500 100 200 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# pkl_C
+#
+DEF pkl_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "pkl_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 100 60 D 40 40 1 1 P
+X ~ 2 0 -100 60 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pkl_C_Small
+#
+DEF pkl_C_Small C 0 10 N N 1 F N
+F0 "C" 10 70 50 H V L CNN
+F1 "pkl_C_Small" 10 -80 50 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 13 -60 -20 60 -20 N
+P 2 0 1 12 -60 20 60 20 N
+X ~ 1 0 100 75 D 40 40 1 1 P
+X ~ 2 0 -100 80 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pkl_LED
+#
+DEF pkl_LED D 0 40 Y N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "pkl_LED" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ LED-3MM
+ LED-5MM
+ LED-10MM
+ LED-0603
+ LED-0805
+ LED-1206
+ LEDV
+$ENDFPLIST
+DRAW
+P 2 0 1 0 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+P 3 0 1 0 65 -40 110 -80 105 -55 N
+P 3 0 1 0 80 -25 125 -65 120 -40 N
+X A A -200 0 150 R 40 40 1 1 P
+X C C 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pkl_R4_Small
+#
+DEF pkl_R4_Small R 0 10 N N 4 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "pkl_R4_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ Resistor_*
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 40 40 1 1 P
+X ~ 2 0 -100 30 U 40 40 1 1 P
+X ~ 3 0 100 30 D 40 40 2 1 P
+X ~ 4 0 -100 30 U 40 40 2 1 P
+X ~ 5 0 100 30 D 40 40 3 1 P
+X ~ 6 0 -100 30 U 40 40 3 1 P
+X ~ 7 0 100 30 D 40 40 4 1 P
+X ~ 8 0 -100 30 U 40 40 4 1 P
+ENDDRAW
+ENDDEF
+#
+# pkl_R_Small
+#
+DEF pkl_R_Small R 0 10 N N 1 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "pkl_R_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ Resistor_*
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 40 40 1 1 P
+X ~ 2 0 -100 30 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pkl_USB_OTG
+#
+DEF pkl_USB_OTG P 0 40 Y Y 1 F N
+F0 "P" 325 -125 50 H V C CNN
+F1 "pkl_USB_OTG" 0 200 50 H V C CNN
+F2 "" -50 -100 60 V V C CNN
+F3 "" -50 -100 60 V V C CNN
+$FPLIST
+ USB*
+$ENDFPLIST
+DRAW
+S -250 -150 250 150 0 1 0 N
+S -205 -150 -195 -120 0 1 0 N
+S -105 -150 -95 -120 0 1 0 N
+S -5 -150 5 -120 0 1 0 N
+S 95 -150 105 -120 0 1 0 N
+S 195 -150 205 -120 0 1 0 N
+X VCC 1 -200 -300 150 U 50 50 1 1 w
+X D- 2 -100 -300 150 U 50 50 1 1 P
+X D+ 3 0 -300 150 U 50 50 1 1 P
+X ID 4 100 -300 150 U 50 50 1 1 W
+X GND 5 200 -300 150 U 50 50 1 1 W
+X shield GND 400 100 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pkl_VREG_5PIN_FIXED
+#
+DEF pkl_VREG_5PIN_FIXED U 0 40 Y Y 1 F N
+F0 "U" -150 -200 60 H V C CNN
+F1 "pkl_VREG_5PIN_FIXED" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -200 150 200 -150 0 1 0 N
+X IN 1 -300 100 100 R 50 50 1 1 W
+X GND 2 300 -100 100 L 50 50 1 1 W
+X EN 3 -300 -100 100 R 50 50 1 1 I
+X BYP 4 -300 0 100 R 50 50 1 1 w
+X OUT 5 300 100 100 L 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# pkl_XTAL_XGXG
+#
+DEF pkl_XTAL_XGXG X 0 40 Y N 1 F N
+F0 "X" 100 100 50 H V C CNN
+F1 "pkl_XTAL_XGXG" 50 -100 50 H V L CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 2 0 1 0 -45 -70 45 -70 N
+P 2 0 1 16 -45 50 -45 -50 N
+P 2 0 1 0 -45 70 45 70 N
+P 2 0 1 16 45 50 45 -50 N
+P 5 0 1 12 -20 40 20 40 20 -40 -20 -40 -20 40 N
+X 1 1 -100 0 55 R 25 20 1 1 P
+X 2 2 100 0 55 L 25 20 1 1 P
+X case GND 0 -100 30 U 10 20 1 1 P
+X case GND 0 100 30 D 10 20 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/hardware/fx2grok-flat/0.2/fx2grok-flat.kicad_pcb b/hardware/fx2grok-flat/0.2/fx2grok-flat.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/hardware/fx2grok-flat/0.2/fx2grok-flat.kicad_pcb
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/hardware/fx2grok-flat/0.2/fx2grok-flat.pro b/hardware/fx2grok-flat/0.2/fx2grok-flat.pro
new file mode 100644
index 0000000..cf0c665
--- /dev/null
+++ b/hardware/fx2grok-flat/0.2/fx2grok-flat.pro
@@ -0,0 +1,79 @@
+update=Fri 15 Sep 2017 05:38:16 PM PDT
+version=1
+last_client=kicad
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=../../../lib/pkl
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=switches
+LibName4=relays
+LibName5=motors
+LibName6=transistors
+LibName7=conn
+LibName8=linear
+LibName9=regul
+LibName10=74xx
+LibName11=cmos4000
+LibName12=adc-dac
+LibName13=memory
+LibName14=xilinx
+LibName15=microcontrollers
+LibName16=dsp
+LibName17=microchip
+LibName18=analog_switches
+LibName19=motorola
+LibName20=texas
+LibName21=intel
+LibName22=audio
+LibName23=interface
+LibName24=digital-audio
+LibName25=philips
+LibName26=display
+LibName27=cypress
+LibName28=siliconi
+LibName29=opto
+LibName30=atmel
+LibName31=contrib
+LibName32=valves
+LibName33=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_conn
+LibName34=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_cypress
+LibName35=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_device
+LibName36=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_ftdi
+LibName37=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_lattice
+LibName38=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_linear
+LibName39=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_logos
+LibName40=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_maxim
+LibName41=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_memory
+LibName42=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_misc
+LibName43=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_molex
+LibName44=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_power
+LibName45=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_sensor
+LibName46=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_silabs
+LibName47=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_tag_connect
+LibName48=/home/esdentem/projects/sigrok/fx2grok-git/lib/pkl/pkl_texas
diff --git a/hardware/fx2grok-flat/0.2/fx2grok-flat.sch b/hardware/fx2grok-flat/0.2/fx2grok-flat.sch
new file mode 100644
index 0000000..72b4e76
--- /dev/null
+++ b/hardware/fx2grok-flat/0.2/fx2grok-flat.sch
@@ -0,0 +1,1306 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:switches
+LIBS:relays
+LIBS:motors
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:pkl_conn
+LIBS:pkl_cypress
+LIBS:pkl_device
+LIBS:pkl_ftdi
+LIBS:pkl_lattice
+LIBS:pkl_linear
+LIBS:pkl_logos
+LIBS:pkl_maxim
+LIBS:pkl_memory
+LIBS:pkl_misc
+LIBS:pkl_molex
+LIBS:pkl_power
+LIBS:pkl_sensor
+LIBS:pkl_silabs
+LIBS:pkl_tag_connect
+LIBS:pkl_texas
+LIBS:fx2grok-flat-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
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