From: Gerhard Sittig <redacted>
Date: Sat, 22 Feb 2020 08:38:32 +0000 (+0100)
Subject: irmp: silence core logic ANALYZE output from the shared library
X-Git-Url: http://sigrok.org/gitweb/?a=commitdiff_plain;ds=sidebyside;h=2a295b87d7f7f9fc8121b9ff61dd3ea430aa5567;p=libsigrokdecode.git

irmp: silence core logic ANALYZE output from the shared library

Workaround the default verbosity level of the IRMP core logic for
PC library build configurations. Silence the ANALYZE related output.
---

diff --git a/irmp/irmp-main-sharedlib.c b/irmp/irmp-main-sharedlib.c
index baa65c9..570df95 100644
--- a/irmp/irmp-main-sharedlib.c
+++ b/irmp/irmp-main-sharedlib.c
@@ -111,6 +111,19 @@ IRMP_DLLEXPORT void irmp_reset_state(void)
 	s_startBitSample = 0;
 	s_curSample = 0;
 	s_end_sample = 0;
+
+	/*
+	 * TODO This is not the most appropriate location to control the
+	 * core logic's verbosity. But out of the public set of library
+	 * routines this call is closest to some initialization routine.
+	 * The query for compile time parameter values is optional, the
+	 * state reset is not. Multiple verbosity setup activities in
+	 * the same program lifetime won't harm. This HACK is clearly
+	 * preferrable over more fiddling with core logic innards, or
+	 * the introduction of yet another DLL routine.
+	 */
+	silent = 1;
+	verbose = 0;
 }
 
 IRMP_DLLEXPORT int irmp_add_one_sample(int sample)