X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=vfd%2Fmax6921%2Fbeagleboard_nixie_cape%2FREADME;h=f6cd92dca55582d84cfbf0c466a73848a95c7ff1;hb=a26d276427a0af78b2f6a660f34b1c54387c53d7;hp=a71a3fa3bcc8617db0c42ac860020c6fabcf8d80;hpb=d7e1285ae4953d0b877cc9ed0603de16f2fde966;p=sigrok-dumps.git

diff --git a/vfd/max6921/beagleboard_nixie_cape/README b/vfd/max6921/beagleboard_nixie_cape/README
index a71a3fa..f6cd92d 100644
--- a/vfd/max6921/beagleboard_nixie_cape/README
+++ b/vfd/max6921/beagleboard_nixie_cape/README
@@ -13,12 +13,12 @@ Logic analyzer setup
 
 The logic analyzer used was Open Bench Logic Sniffer (at 10Mhz):
 
- Probe		MAX6921 Pin
+ Probe          MAX6921 Pin
  --------------------------
- 0              LOAD	
- 1		DATA
- 2		CLK
- 3		BLANK (PWM Brightness Control)
+ 0              LOAD    
+ 1              DATA
+ 2              CLK
+ 3              BLANK (PWM Brightness Control)
 
 Data
 ----