X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Frigol-ds%2Fprotocol.c;h=26b492053b653a72a92d2dd3866a6db81e5405e7;hb=a90ffc373005b8ee506e5b69bcb9451233295d1b;hp=8e12990173dbe8e5e95c82122e127c534fd5c499;hpb=55bece00aae2a53a0e25a685ee3ca111dc29fd12;p=libsigrok.git

diff --git a/src/hardware/rigol-ds/protocol.c b/src/hardware/rigol-ds/protocol.c
index 8e129901..26b49205 100644
--- a/src/hardware/rigol-ds/protocol.c
+++ b/src/hardware/rigol-ds/protocol.c
@@ -333,12 +333,17 @@ SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
 	struct dev_context *devc;
 	gchar *trig_mode;
 	unsigned int num_channels, i, j;
+	int buffer_samples;
 
 	if (!(devc = sdi->priv))
 		return SR_ERR;
 
-	sr_dbg("Starting data capture for frameset %" PRIu64 " of %" PRIu64,
-	       devc->num_frames + 1, devc->limit_frames);
+	if (devc->limit_frames == 0)
+		sr_dbg("Starting data capture for frameset %" PRIu64,
+		       devc->num_frames + 1);
+	else
+		sr_dbg("Starting data capture for frameset %" PRIu64 " of %"
+		       PRIu64, devc->num_frames + 1, devc->limit_frames);
 
 	switch (devc->model->series->protocol) {
 	case PROTOCOL_V1:
@@ -394,12 +399,29 @@ SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
 					}
 				}
 
-				devc->analog_frame_size = devc->digital_frame_size =
-					num_channels == 1 ?
-						devc->model->series->buffer_samples :
-							num_channels == 2 ?
-								devc->model->series->buffer_samples / 2 :
-								devc->model->series->buffer_samples / 4;
+				buffer_samples = devc->model->series->buffer_samples;
+				if (buffer_samples == 0)
+				{
+					/* The DS4000 series does not have a fixed memory depth, it
+					 * can be chosen from the menu and also varies with number
+					 * of active channels. Retrieve the actual number with the
+					 * ACQ:MDEP command. */
+					sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
+					devc->analog_frame_size = devc->digital_frame_size =
+							buffer_samples;
+				}
+				else
+				{
+					/* The DS1000Z series has a fixed memory depth which we
+					 * need to divide correctly according to the number of
+					 * active channels. */
+					devc->analog_frame_size = devc->digital_frame_size =
+						num_channels == 1 ?
+							buffer_samples :
+								num_channels == 2 ?
+									buffer_samples / 2 :
+									buffer_samples / 4;
+				}
 			}
 
 			if (rigol_ds_config_set(sdi, ":SING") != SR_OK)
@@ -879,7 +901,8 @@ SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
 	sr_dbg("Current trigger source %s", devc->trigger_source);
 
 	/* Horizontal trigger position. */
-	if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK)
+	if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str,
+			&devc->horiz_triggerpos) != SR_OK)
 		return SR_ERR;
 	sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);