X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fopenbench-logic-sniffer%2Fapi.c;h=93fa3bd7e57618209b19655f65aed554df708c29;hb=c3cd66a00cdb4afbd43108563d979eebfbafaf69;hp=1e22c5b82f97970c9a83e00c36419d47071ad583;hpb=bee2b0168c087676c1b365861d8c2d4714afa9b9;p=libsigrok.git

diff --git a/src/hardware/openbench-logic-sniffer/api.c b/src/hardware/openbench-logic-sniffer/api.c
index 1e22c5b8..93fa3bd7 100644
--- a/src/hardware/openbench-logic-sniffer/api.c
+++ b/src/hardware/openbench-logic-sniffer/api.c
@@ -126,14 +126,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 	if (serial_open(serial, SERIAL_RDWR) != SR_OK)
 		return NULL;
 
-	ret = SR_OK;
-	for (i = 0; i < 5; i++) {
-		if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
-			sr_err("Port %s is not writable.", conn);
-			break;
-		}
-	}
-	if (ret != SR_OK) {
+	if (ols_send_reset(serial) != SR_OK) {
 		serial_close(serial);
 		sr_err("Could not use port %s. Quitting.", conn);
 		return NULL;
@@ -244,9 +237,6 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd
 
 	(void)cg;
 
-	if (sdi->status != SR_ST_ACTIVE)
-		return SR_ERR_DEV_CLOSED;
-
 	devc = sdi->priv;
 
 	switch (key) {
@@ -446,9 +436,6 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 	int num_ols_changrp;
 	int ret, i;
 
-	if (sdi->status != SR_ST_ACTIVE)
-		return SR_ERR_DEV_CLOSED;
-
 	devc = sdi->priv;
 	serial = sdi->conn;
 
@@ -480,6 +467,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 		return SR_ERR;
 	}
 	if (devc->num_stages > 0) {
+		/*
+		 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
+		 * reset command must be send prior each arm command
+		 */
+		sr_dbg("Send reset command before trigger configure");
+		if (ols_send_reset(serial) != SR_OK)
+			return SR_ERR;
+
 		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
 		devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
 		for (i = 0; i <= devc->num_stages; i++) {