X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.h;h=f1eb16ec2598827b9221d4b60cc7f0129a16a61f;hb=9b4d261fabf7f9fd70ccd7514ecdadb8e87a7490;hp=edace1e54970492978d348b50e280730a745c1d4;hpb=07411a605ed83f7a57db9d805731c0abe5893df7;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h index edace1e5..f1eb16ec 100644 --- a/src/hardware/asix-sigma/protocol.h +++ b/src/hardware/asix-sigma/protocol.h @@ -53,6 +53,44 @@ enum asix_device_type { ASIX_TYPE_OMEGA, }; +/* + * FPGA commands are 8bits wide. The upper nibble is a command opcode, + * the lower nibble can carry operand values. 8bit register addresses + * and 8bit data values get communicated in two steps. + */ + +/* Register access. */ +#define REG_ADDR_LOW (0x0 << 4) +#define REG_ADDR_HIGH (0x1 << 4) +#define REG_DATA_LOW (0x2 << 4) +#define REG_DATA_HIGH_WRITE (0x3 << 4) +#define REG_READ_ADDR (0x4 << 4) +#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */ +#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */ +#define REG_ADDR_INC (REG_ADDR_ADJUST) +#define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) + +/* Sample memory access. */ +#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ +#define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ +#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ +#define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ +#define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ +#define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) + +/* + * Registers at a specific address can have different meanings depending + * on whether data is read or written. This is why direction is part of + * the programming language identifiers. + * + * The vendor documentation suggests that in addition to the first 16 + * register addresses which implement the logic analyzer's feature set, + * there are 240 more registers in the 16 to 255 address range which + * are available to applications and plugin features. Can libsigrok's + * asix-sigma driver store configuration data there, to avoid expensive + * operations (think: firmware re-load). + */ + enum sigma_write_register { WRITE_CLOCK_SELECT = 0, WRITE_TRIGGER_SELECT = 1, @@ -85,39 +123,9 @@ enum sigma_read_register { READ_TEST = 15, }; -/* - * FPGA commands are 8bits wide. The upper nibble is a command opcode, - * the lower nibble can carry operand values. 8bit register addresses - * and 8bit data values get communicated in two steps. - */ - -/* Register access. */ -#define REG_ADDR_LOW (0x0 << 4) -#define REG_ADDR_HIGH (0x1 << 4) -#define REG_DATA_LOW (0x2 << 4) -#define REG_DATA_HIGH_WRITE (0x3 << 4) -#define REG_READ_ADDR (0x4 << 4) -#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */ -#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */ -#define REG_ADDR_INC (REG_ADDR_ADJUST) -#define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) - -/* Sample memory access. */ -#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ -#define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ -#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ -#define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ -#define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ -#define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) - #define LEDSEL0 6 #define LEDSEL1 7 - -#define EVENTS_PER_CLUSTER 7 - -#define CHUNK_SIZE 1024 - /* WRITE_MODE register fields. */ #define WMR_SDRAMWRITEEN (1 << 0) #define WMR_SDRAMREADEN (1 << 1) @@ -142,8 +150,16 @@ enum sigma_read_register { * Layout of the sample data DRAM, which will be downloaded to the PC: * * Sigma memory is organized in 32K rows. Each row contains 64 clusters. - * Each cluster contains a timestamp (16bit) and 7 samples (16bits each). - * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MB (256 Mbit). + * Each cluster contains a timestamp (16bit) and 7 events (16bits each). + * Events contain 16 bits of sample data (potentially taken at multiple + * sample points, see below). + * + * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The + * size of a memory row is 1024 bytes. Assuming x16 organization of the + * memory array, address specs (sample count, trigger position) are kept + * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit + * refer to the "event" within the row. Because there is one timestamp for + * seven events each, one memory row can hold up to 64x7 == 448 events. * * Sample data is represented in 16bit quantities. The first sample in * the cluster corresponds to the cluster's timestamp. Each next sample @@ -151,33 +167,35 @@ enum sigma_read_register { * one sample period, according to the samplerate). In the absence of * pin level changes, no data is provided (RLE compression). A cluster * is enforced for each 64K ticks of the timestamp, to reliably handle - * rollover and determination of the next timestamp of the next cluster. + * rollover and determine the next timestamp of the next cluster. * + * For samplerates up to 50MHz, an event directly translates to one set + * of sample data at a single sample point, spanning up to 16 channels. * For samplerates of 100MHz, there is one 16 bit entity for each 20ns * period (50MHz rate). The 16 bit memory contains 2 samples of up to * 8 channels. Bits of multiple samples are interleaved. For samplerates * of 200MHz one 16bit entity contains 4 samples of up to 4 channels, * each 5ns apart. - * - * Memory addresses (sample count, trigger position) are kept in 24bit - * entities. The upper 15 bit refer to the "row", the lower 9 bit refer - * to the "event" within the row. Because there is one timestamp for - * seven samples each, one memory row can hold up to 64x7 == 448 samples. */ -/* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */ -struct sigma_dram_cluster { - uint8_t timestamp_lo; - uint8_t timestamp_hi; - struct { - uint8_t sample_hi; - uint8_t sample_lo; - } samples[7]; -}; +#define ROW_COUNT 32768 +#define ROW_LENGTH_BYTES 1024 +#define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t)) +#define ROW_SHIFT 9 /* log2 of u16 count */ +#define ROW_MASK ((1UL << ROW_SHIFT) - 1) +#define EVENTS_PER_CLUSTER 7 +#define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER)) +#define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER) -/* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */ struct sigma_dram_line { - struct sigma_dram_cluster cluster[64]; + struct sigma_dram_cluster { + uint8_t timestamp_lo; + uint8_t timestamp_hi; + struct sigma_dram_event { + uint8_t sample_hi; + uint8_t sample_lo; + } samples[EVENTS_PER_CLUSTER]; + } cluster[CLUSTERS_PER_ROW]; }; struct clockselect_50 { @@ -266,6 +284,7 @@ enum triggerfunc { struct sigma_state { enum { SIGMA_UNINITIALIZED = 0, + SIGMA_CONFIG, SIGMA_IDLE, SIGMA_CAPTURE, SIGMA_STOPPING, @@ -275,6 +294,17 @@ struct sigma_state { uint16_t lastsample; }; +enum sigma_firmware_idx { + SIGMA_FW_NONE, + SIGMA_FW_50MHZ, + SIGMA_FW_100MHZ, + SIGMA_FW_200MHZ, + SIGMA_FW_SYNC, + SIGMA_FW_FREQ, +}; + +struct submit_buffer; + struct dev_context { struct { uint16_t vid, pid; @@ -283,33 +313,35 @@ struct dev_context { enum asix_device_type type; } id; struct ftdi_context ftdic; - uint64_t cur_samplerate; - uint64_t limit_msec; - uint64_t limit_samples; - uint64_t sent_samples; - uint64_t start_time; - int cur_firmware; + uint64_t samplerate; + struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */ + struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */ + struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */ + enum sigma_firmware_idx firmware_idx; int num_channels; - int cur_channels; int samples_per_event; uint64_t capture_ratio; struct sigma_trigger trigger; int use_triggers; struct sigma_state state; + struct submit_buffer *buffer; }; extern SR_PRIV const uint64_t samplerates[]; extern SR_PRIV const size_t samplerates_count; -SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, - struct dev_context *devc); -SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc); -SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc); -SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, - uint64_t limit_samples); -SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate); +SR_PRIV int sigma_write_register(struct dev_context *devc, + uint8_t reg, uint8_t *data, size_t len); +SR_PRIV int sigma_set_register(struct dev_context *devc, + uint8_t reg, uint8_t value); +SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, + struct triggerlut *lut); +SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate); +SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi); +SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc); SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); -SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc); +SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, + struct triggerlut *lut); #endif