X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.c;h=3a653939f7a11c4f44a2ccee951933e341a88c9f;hb=3d9373af2ecfb4c2f74b68ad828617fd02519ca6;hp=6051c6b75e74bd6e3404251545d4feaff53ff6e5;hpb=7dd766e0aaec62f6f25d522919e6f4df599c6171;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c index 6051c6b7..3a653939 100644 --- a/src/hardware/asix-sigma/protocol.c +++ b/src/hardware/asix-sigma/protocol.c @@ -382,7 +382,7 @@ static int sigma_read_pos(struct dev_context *devc, } static int sigma_read_dram(struct dev_context *devc, - uint16_t startchunk, size_t numchunks, uint8_t *data) + size_t startchunk, size_t numchunks, uint8_t *data) { uint8_t buf[128], *wrptr, regval; size_t chunk; @@ -432,10 +432,11 @@ static int sigma_read_dram(struct dev_context *devc, SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, struct triggerlut *lut) { - int lut_addr; + size_t lut_addr; uint16_t bit; uint8_t m3d, m2d, m1d, m0d; - uint8_t buf[6], *wrptr, regval; + uint8_t buf[6], *wrptr, v8; + uint16_t selreg; int ret; /* @@ -453,7 +454,7 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, m3d |= 1 << 2; if (lut->m3s & bit) m3d |= 1 << 1; - if (lut->m3 & bit) + if (lut->m3q & bit) m3d |= 1 << 0; /* M2D3 M2D2 M2D1 M2D0 */ @@ -502,9 +503,9 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, buf, wrptr - buf); if (ret != SR_OK) return ret; - ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, - TRGSEL2_RESET | TRGSEL2_LUT_WRITE | - (lut_addr & TRGSEL2_LUT_ADDR_MASK)); + v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE | + (lut_addr & TRGSEL2_LUT_ADDR_MASK); + ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8); if (ret != SR_OK) return ret; } @@ -513,16 +514,14 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, * Send the parameters. This covers counters and durations. */ wrptr = buf; - regval = 0; - regval |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT; - regval |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT; - write_u8_inc(&wrptr, regval); - regval = 0; - regval |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT; - regval |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT; - regval |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT; - regval |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT; - write_u8_inc(&wrptr, regval); + selreg = 0; + selreg |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT; + selreg |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT; + selreg |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT; + selreg |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT; + selreg |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT; + selreg |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT; + write_u16be_inc(&wrptr, selreg); write_u16be_inc(&wrptr, lut->params.cmpb); write_u16be_inc(&wrptr, lut->params.cmpa); ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); @@ -602,7 +601,8 @@ static int sigma_fpga_init_bitbang_once(struct dev_context *devc) BB_PIN_CCLK, BB_PIN_CCLK, }; - int retries, ret; + size_t retries; + int ret; uint8_t data; /* Section 2. part 1), do the FPGA suicide. */ @@ -747,7 +747,7 @@ static int sigma_fpga_init_la(struct dev_context *devc) * by the caller of this function. */ static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, - uint8_t **bb_cmd, gsize *bb_cmd_size) + uint8_t **bb_cmd, size_t *bb_cmd_size) { uint8_t *firmware; size_t file_size; @@ -944,7 +944,7 @@ SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) g_variant_unref(data); count_msecs = 0; if (user_count) - count_msecs = 1000 * user_count / devc->samplerate + 1; + count_msecs = 1000 * user_count / devc->clock.samplerate + 1; /* Get time limit, which is in msecs. */ ret = sr_sw_limits_config_get(&devc->cfg_limits, @@ -964,7 +964,7 @@ SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) return SR_OK; /* Add some slack, and use that timeout for acquisition. */ - worst_cluster_time_ms = 1000 * 65536 / devc->samplerate; + worst_cluster_time_ms = 1000 * 65536 / devc->clock.samplerate; acquire_msecs += 2 * worst_cluster_time_ms; data = g_variant_new_uint64(acquire_msecs); ret = sr_sw_limits_config_set(&devc->acq_limits, @@ -1015,11 +1015,51 @@ SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate) return SR_ERR_ARG; } -SR_PRIV uint64_t sigma_get_samplerate(const struct sr_dev_inst *sdi) +/* Gets called at probe time. Can seed software settings from hardware state. */ +SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi) { - /* TODO Retrieve value from hardware. */ + struct dev_context *devc; + int ret; + uint8_t regaddr, regval; + + devc = sdi->priv; + if (!devc) + return SR_ERR_ARG; + + /* Seed configuration values from defaults. */ + devc->firmware_idx = SIGMA_FW_NONE; + devc->clock.samplerate = samplerates[0]; + + /* TODO + * Ideally the device driver could retrieve recently stored + * details from hardware registers, thus re-use user specified + * configuration values across sigrok sessions. Which could + * avoid repeated expensive though unnecessary firmware uploads, + * improve performance and usability. Unfortunately it appears + * that the registers range which is documented as available for + * application use keeps providing 0xff data content. At least + * with the netlist version which ships with sigrok. The same + * was observed with unused registers in the first page. + */ + return SR_ERR_NA; + + /* This is for research, currently does not work yet. */ + ret = sigma_check_open(sdi); + regaddr = 16; + regaddr = 14; + ret = sigma_set_register(devc, regaddr, 'F'); + ret = sigma_get_register(devc, regaddr, ®val); + sr_warn("%s() reg[%u] val[%u] rc[%d]", __func__, regaddr, regval, ret); + ret = sigma_check_close(devc); + return ret; +} + +/* Gets called after successful (volatile) hardware configuration. */ +SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi) +{ + /* TODO See above, registers seem to not hold written data. */ (void)sdi; - return samplerates[0]; + return SR_ERR_NA; } SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) @@ -1028,13 +1068,13 @@ SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) struct drv_context *drvc; uint64_t samplerate; int ret; - int num_channels; + size_t num_channels; devc = sdi->priv; drvc = sdi->driver->context; /* Accept any caller specified rate which the hardware supports. */ - ret = sigma_normalize_samplerate(devc->samplerate, &samplerate); + ret = sigma_normalize_samplerate(devc->clock.samplerate, &samplerate); if (ret != SR_OK) return ret; @@ -1065,6 +1105,14 @@ SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) devc->samples_per_event = 16 / devc->num_channels; } + /* + * Store the firmware type and most recently configured samplerate + * in hardware, such that subsequent sessions can start from there. + * This is a "best effort" approach. Failure is non-fatal. + */ + if (ret == SR_OK) + (void)sigma_store_hw_config(sdi); + return ret; } @@ -1241,7 +1289,8 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) struct sr_trigger_stage *stage; struct sr_trigger_match *match; const GSList *l, *m; - int channelbit, trigger_set; + uint16_t channelbit; + size_t trigger_set; devc = sdi->priv; memset(&devc->trigger, 0, sizeof(devc->trigger)); @@ -1258,7 +1307,7 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) if (!match->channel->enabled) continue; channelbit = 1 << match->channel->index; - if (devc->samplerate >= SR_MHZ(100)) { + if (devc->clock.samplerate >= SR_MHZ(100)) { /* Fast trigger support. */ if (trigger_set) { sr_err("100/200MHz modes limited to single trigger pin."); @@ -1311,7 +1360,7 @@ static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, struct sigma_trigger *t) { const uint8_t *rdptr; - int i; + size_t i; uint16_t sample; rdptr = samples; @@ -1446,7 +1495,8 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, { struct sigma_state *ss; uint16_t tsdiff, ts, sample, item16; - unsigned int i; + size_t count; + size_t evt; if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER) triggered = FALSE; @@ -1465,7 +1515,6 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, ts = sigma_dram_cluster_ts(dram_cluster); tsdiff = ts - ss->lastts; if (tsdiff > 0) { - size_t count; sample = ss->lastsample; count = tsdiff * devc->samples_per_event; (void)check_and_submit_sample(devc, sample, count, FALSE); @@ -1480,9 +1529,9 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, * buffer depth is neither assumed nor required here. */ sample = 0; - for (i = 0; i < events_in_cluster; i++) { - item16 = sigma_dram_cluster_data(dram_cluster, i); - if (devc->samplerate == SR_MHZ(200)) { + for (evt = 0; evt < events_in_cluster; evt++) { + item16 = sigma_dram_cluster_data(dram_cluster, evt); + if (devc->clock.samplerate == SR_MHZ(200)) { sample = sigma_deinterlace_200mhz_data(item16, 0); check_and_submit_sample(devc, sample, 1, triggered); sample = sigma_deinterlace_200mhz_data(item16, 1); @@ -1491,7 +1540,7 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, check_and_submit_sample(devc, sample, 1, triggered); sample = sigma_deinterlace_200mhz_data(item16, 3); check_and_submit_sample(devc, sample, 1, triggered); - } else if (devc->samplerate == SR_MHZ(100)) { + } else if (devc->clock.samplerate == SR_MHZ(100)) { sample = sigma_deinterlace_100mhz_data(item16, 0); check_and_submit_sample(devc, sample, 1, triggered); sample = sigma_deinterlace_100mhz_data(item16, 1); @@ -1518,19 +1567,19 @@ static int decode_chunk_ts(struct dev_context *devc, size_t events_in_line, size_t trigger_event) { struct sigma_dram_cluster *dram_cluster; - unsigned int clusters_in_line; - unsigned int events_in_cluster; - unsigned int i; - uint32_t trigger_cluster; + size_t clusters_in_line; + size_t events_in_cluster; + size_t cluster; + size_t trigger_cluster; clusters_in_line = events_in_line; clusters_in_line += EVENTS_PER_CLUSTER - 1; clusters_in_line /= EVENTS_PER_CLUSTER; - trigger_cluster = ~0; /* Check if trigger is in this chunk. */ + trigger_cluster = ~0UL; if (trigger_event < EVENTS_PER_ROW) { - if (devc->samplerate <= SR_MHZ(50)) { + if (devc->clock.samplerate <= SR_MHZ(50)) { trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, trigger_event); } @@ -1540,11 +1589,11 @@ static int decode_chunk_ts(struct dev_context *devc, } /* For each full DRAM cluster. */ - for (i = 0; i < clusters_in_line; i++) { - dram_cluster = &dram_line->cluster[i]; + for (cluster = 0; cluster < clusters_in_line; cluster++) { + dram_cluster = &dram_line->cluster[cluster]; /* The last cluster might not be full. */ - if ((i == clusters_in_line - 1) && + if ((cluster == clusters_in_line - 1) && (events_in_line % EVENTS_PER_CLUSTER)) { events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; } else { @@ -1552,7 +1601,7 @@ static int decode_chunk_ts(struct dev_context *devc, } sigma_decode_dram_cluster(devc, dram_cluster, - events_in_cluster, i == trigger_cluster); + events_in_cluster, cluster == trigger_cluster); } return SR_OK; @@ -1566,11 +1615,11 @@ static int download_capture(struct sr_dev_inst *sdi) struct sigma_dram_line *dram_line; uint32_t stoppos, triggerpos; uint8_t modestatus; - uint32_t i; - uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; - uint32_t dl_first_line, dl_line; - uint32_t dl_events_in_line, trigger_event; - uint32_t trg_line, trg_event; + size_t line_idx; + size_t dl_lines_total, dl_lines_curr, dl_lines_done; + size_t dl_first_line, dl_line; + size_t dl_events_in_line, trigger_event; + size_t trg_line, trg_event; int ret; devc = sdi->priv; @@ -1607,8 +1656,8 @@ static int download_capture(struct sr_dev_inst *sdi) sr_err("Could not query capture positions/state."); return FALSE; } - trg_line = ~0; - trg_event = ~0; + trg_line = ~0UL; + trg_event = ~0UL; if (modestatus & RMR_TRIGGERED) { trg_line = triggerpos >> ROW_SHIFT; trg_event = triggerpos & ROW_MASK; @@ -1658,18 +1707,18 @@ static int download_capture(struct sr_dev_inst *sdi) devc->state.lastsample = 0; } - for (i = 0; i < dl_lines_curr; i++) { + for (line_idx = 0; line_idx < dl_lines_curr; line_idx++) { /* The last "DRAM line" need not span its full length. */ dl_events_in_line = EVENTS_PER_ROW; - if (dl_lines_done + i == dl_lines_total - 1) + if (dl_lines_done + line_idx == dl_lines_total - 1) dl_events_in_line = stoppos & ROW_MASK; /* Test if the trigger happened on this line. */ - trigger_event = ~0; - if (dl_lines_done + i == trg_line) + trigger_event = ~0UL; + if (dl_lines_done + line_idx == trg_line) trigger_event = trg_event; - decode_chunk_ts(devc, dram_line + i, + decode_chunk_ts(devc, dram_line + line_idx, dl_events_in_line, trigger_event); } @@ -1775,9 +1824,9 @@ static void build_lut_entry(uint16_t *lut_entry, /* Add a logical function to LUT mask. */ static void add_trigger_function(enum triggerop oper, enum triggerfunc func, - int index, int neg, uint16_t *mask) + size_t index, gboolean neg, uint16_t *mask) { - int i, j; + size_t i, j; int x[2][2], tmp, a, b, aset, bset, rset; memset(x, 0, sizeof(x)); @@ -1864,13 +1913,13 @@ SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, struct triggerlut *lut) { uint16_t masks[2]; - int bitidx, condidx; + size_t bitidx, condidx; uint16_t value, mask; /* Start assuming simple triggers. */ memset(lut, 0, sizeof(*lut)); lut->m4 = 0xa000; - lut->m3 = 0xffff; + lut->m3q = 0xffff; /* Process value/mask triggers. */ value = devc->trigger.simplevalue; @@ -1896,19 +1945,22 @@ SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, /* Add glue logic for rise/fall triggers. */ if (masks[0] || masks[1]) { - lut->m3 = 0; + lut->m3q = 0; if (masks[0] & devc->trigger.risingmask) - add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); + add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3q); if (masks[0] & devc->trigger.fallingmask) - add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); + add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3q); if (masks[1] & devc->trigger.risingmask) - add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); + add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3q); if (masks[1] & devc->trigger.fallingmask) - add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); + add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3q); } /* Triggertype: event. */ - lut->params.selres = 3; + lut->params.selres = TRGSEL_SELCODE_NEVER; + lut->params.selinc = TRGSEL_SELCODE_LEVEL; + lut->params.sela = 0; /* Counter >= CMPA && LEVEL */ + lut->params.cmpa = 0; /* Count 0 -> 1 already triggers. */ return SR_OK; }