X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=sainsmart_dds120.c;h=e4ba51c4834fb8653b0140983f25f208e127fa4a;hb=e1c5ba21853765725d723efdef22bedef7cfecc6;hp=a854f8d01ec80c0c6f1d22b05ebeffa02d4adb41;hpb=24373950c5858ea7761ac8aa77b51c717558316b;p=sigrok-firmware-fx2lafw.git
diff --git a/sainsmart_dds120.c b/sainsmart_dds120.c
index a854f8d0..e4ba51c4 100644
--- a/sainsmart_dds120.c
+++ b/sainsmart_dds120.c
@@ -15,8 +15,7 @@
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ * License along with this library; if not, see .
*/
#include
@@ -25,9 +24,27 @@
#include
#include
+#define SET_ANALOG_MODE() PA7 = 1
+
+/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
+/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
+#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
+
+#define LED_CLEAR() NOP
+#define LED_GREEN() NOP
+#define LED_RED() NOP
+
+/* CTLx pin index (IFCLK, ADC clock input). */
+#define CTL_BIT 2
+
+#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
+#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */
+
/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;
+static volatile WORD ledcounter = 0;
+
static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;
@@ -65,13 +82,19 @@ void suspend_isr(void) __interrupt SUSPEND_ISR
void timer2_isr(void) __interrupt TF2_ISR
{
- /* Toggle the 1kHz pin, only accurate up to ca 8MHz */
- IOE = IOE^0x04;
+ TOGGLE_CALIBRATION_PIN();
+
+ if (ledcounter && (--ledcounter == 0))
+ LED_CLEAR();
+
TF2 = 0;
}
/**
- * The gain stage is 2 stage approach. -6dB and -20dB on the first stage (attentuator). The second stage is then doing the gain by 3 different resistor values switched into the feedback loop.
+ * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
+ * (attentuator). The second stage is then doing the gain by 3 different
+ * resistor values switched into the feedback loop.
+ *
* #Channel 0:
* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
@@ -79,6 +102,7 @@ void timer2_isr(void) __interrupt TF2_ISR
* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
+ *
* #Channel 1:
* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
@@ -150,7 +174,6 @@ static BOOL set_voltage(BYTE channel, BYTE val)
return TRUE;
}
-
/**
* Each LSB in the nibble of the byte controls the coupling per channel.
*
@@ -206,6 +229,8 @@ static void start_sampling(void)
{
int i;
+ SET_ANALOG_MODE();
+
clear_fifo();
for (i = 0; i < 1000; i++);
@@ -219,6 +244,9 @@ static void start_sampling(void)
GPIFTCB0 = 0;
GPIFTRIG = (altiface == 0) ? 6 : 4;
+ /* Set green LED, don't clear LED afterwards (ledcounter = 0). */
+ LED_GREEN();
+ ledcounter = 0;
}
static void select_interface(BYTE alt)
@@ -258,21 +286,21 @@ static const struct samplerate_info {
} samplerates[] = {
{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
- { 24, 1, 0, 2, 1, 0x40, 0xea },
- { 16, 1, 1, 2, 0, 0x40, 0xea },
- { 15, 1, 0, 2, 1, 0x40, 0xaa },
- { 12, 2, 1, 2, 0, 0x40, 0xea },
- { 11, 1, 1, 2, 0, 0x40, 0xaa },
- { 8, 3, 2, 2, 0, 0x40, 0xea },
- { 6, 2, 2, 2, 0, 0x40, 0xaa },
- { 5, 3, 2, 2, 0, 0x40, 0xaa },
- { 4, 6, 5, 2, 0, 0x40, 0xea },
- { 3, 5, 4, 2, 0, 0x40, 0xaa },
- { 2, 12, 11, 2, 0, 0x40, 0xea },
- { 1, 24, 23, 2, 0, 0x40, 0xea },
- { 50, 48, 47, 2, 0, 0x40, 0xea },
- { 20, 120, 119, 2, 0, 0x40, 0xea },
- { 10, 240, 239, 2, 0, 0x40, 0xea },
+ { 24, 1, 0, 2, 1, OUT0, 0xea },
+ { 16, 1, 1, 2, 0, OUT0, 0xea },
+ { 15, 1, 0, 2, 1, OUT0, 0xaa },
+ { 12, 2, 1, 2, 0, OUT0, 0xea },
+ { 11, 1, 1, 2, 0, OUT0, 0xaa },
+ { 8, 3, 2, 2, 0, OUT0, 0xea },
+ { 6, 2, 2, 2, 0, OUT0, 0xaa },
+ { 5, 3, 2, 2, 0, OUT0, 0xaa },
+ { 4, 6, 5, 2, 0, OUT0, 0xea },
+ { 3, 5, 4, 2, 0, OUT0, 0xaa },
+ { 2, 12, 11, 2, 0, OUT0, 0xea },
+ { 1, 24, 23, 2, 0, OUT0, 0xea },
+ { 50, 48, 47, 2, 0, OUT0, 0xea },
+ { 20, 120, 119, 2, 0, OUT0, 0xea },
+ { 10, 240, 239, 2, 0, OUT0, 0xea },
};
static BOOL set_samplerate(BYTE rate)
@@ -293,16 +321,18 @@ static BOOL set_samplerate(BYTE rate)
/*
* The program for low-speed, e.g. 1 MHz, is:
- * wait 24, CTL2=0, FIFO
- * wait 23, CTL2=1
- * jump 0, CTL2=1
+ * wait 24, CTLx=0, FIFO
+ * wait 23, CTLx=1
+ * jump 0, CTLx=1
*
* The program for 24 MHz is:
- * wait 1, CTL2=0, FIFO
- * jump 0, CTL2=1
+ * wait 1, CTLx=0, FIFO
+ * jump 0, CTLx=1
*
* The program for 30/48 MHz is:
- * jump 0, CTL2=Z, FIFO, LOOP
+ * jump 0, CTLx=Z, FIFO, LOOP
+ *
+ * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
*/
/* LENGTH / BRANCH 0-7 */
@@ -327,8 +357,8 @@ static BOOL set_samplerate(BYTE rate)
/* OUTPUT 0-7 */
EXTAUTODAT2 = samplerates[i].out0;
- EXTAUTODAT2 = 0x44; /* OE0=1, CTL0=1 */
- EXTAUTODAT2 = 0x44; /* OE0=1, CTL0=1 */
+ EXTAUTODAT2 = OE_CTL;
+ EXTAUTODAT2 = OE_CTL;
EXTAUTODAT2 = 0;
EXTAUTODAT2 = 0;
EXTAUTODAT2 = 0;
@@ -356,18 +386,18 @@ static BOOL set_calibration_pulse(BYTE fs)
switch (fs) {
case 0: // 100Hz
RCAP2L = -10000 & 0xff;
- RCAP2H = (-10000 >> 8) & 0xff;
+ RCAP2H = (-10000 & 0xff00) >> 8;
return TRUE;
case 1: // 1kHz
RCAP2L = -1000 & 0xff;
- RCAP2H = (-1000 >> 8) & 0xff;
+ RCAP2H = (-1000 & 0xff00) >> 8;
return TRUE;
case 10: // 1kHz
- RCAP2L = -100 & 0xff;
+ RCAP2L = (BYTE)(-100 & 0xff);
RCAP2H = 0xff;
return TRUE;
case 50: // 50kHz
- RCAP2L = -20 & 0xff;
+ RCAP2L = (BYTE)(-20 & 0xff);
RCAP2H = 0xff;
return TRUE;
default:
@@ -417,6 +447,10 @@ BOOL handle_vendorcommand(BYTE cmd)
{
stop_sampling();
+ /* Set red LED, clear after timeout. */
+ LED_RED();
+ ledcounter = 1000;
+
/* Clear EP0BCH/L for each valid command. */
if (cmd >= 0xe0 && cmd <= 0xe6) {
EP0BCH = 0;
@@ -455,6 +489,8 @@ static void init(void)
EP4CFG = 0;
EP8CFG = 0;
+ SET_ANALOG_MODE();
+
/* In idle mode tristate all outputs. */
GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
@@ -491,21 +527,21 @@ static void main(void)
/* Init timer2. */
RCAP2L = -1000 & 0xff;
- RCAP2H = (-1000 >> 8) & 0xff;
+ RCAP2H = (-1000 & 0xff00) >> 8;
T2CON = 0;
ET2 = 1;
TR2 = 1;
RENUMERATE_UNCOND();
+ PORTECFG = 0;
PORTCCFG = 0;
PORTACFG = 0;
- PORTECFG = 0;
- OEE = 0xFF;
+ OEE = 0xff;
OEC = 0xff;
- OEA = 0x80;
+ OEA = 0xff;
- PA7 = 1;
+ SET_ANALOG_MODE();
while (TRUE) {
if (dosud) {
@@ -517,7 +553,7 @@ static void main(void)
dosuspend = FALSE;
do {
/* Make sure ext wakeups are cleared. */
- WAKEUPCS |= bmWU|bmWU2;
+ WAKEUPCS |= bmWU | bmWU2;
SUSPEND = 1;
PCON |= 1;
__asm