X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=i2s%2F2ch-16bit-16khz%2FREADME;h=5403a16286166684201a9ceb40eaac084e71ea78;hb=01e11948c0816f05849c772304154b4741f15c47;hp=2c24397ce912c1ff24c9c8701c71d587fa1b7b4b;hpb=fb21eed8341bf0c1063d3dce03d1da980e555bbe;p=sigrok-dumps.git

diff --git a/i2s/2ch-16bit-16khz/README b/i2s/2ch-16bit-16khz/README
index 2c24397..5403a16 100644
--- a/i2s/2ch-16bit-16khz/README
+++ b/i2s/2ch-16bit-16khz/README
@@ -8,7 +8,7 @@ shipping forecast through one channel, and the other channel disconnected.
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a EE Electronics ESLA201A at a 
+The logic analyzer used for capturing was a EE Electronics ESLA201A at a
 sample rate of 16MHz. The logic analyzer probes were connected to the I2S
 pins like this:
 
@@ -17,3 +17,4 @@ pins like this:
   0           Clock
   1           Frame Select
   2           Data
+