X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=hardware%2Frigol-ds%2Fapi.c;h=4fc0cd17b11984bc3756315bc2a2398c450a925c;hb=aff00e40880184c9f9d4a934d83af0cf052ed70c;hp=52c72a4451d9e798cddab38d9d62bde48dc0bec4;hpb=fcdebbe89cca239c2270bea97ee709d26c51ae3b;p=libsigrok.git diff --git a/hardware/rigol-ds/api.c b/hardware/rigol-ds/api.c index 52c72a44..4fc0cd17 100644 --- a/hardware/rigol-ds/api.c +++ b/hardware/rigol-ds/api.c @@ -156,47 +156,74 @@ static const char *data_sources[] = { "Segmented", }; -/* - * name, series, protocol flavor, min timebase, max timebase, min vdiv, - * digital channels, number of horizontal divs - */ +enum vendor { + RIGOL, + AGILENT, +}; + +enum series { + VS5000, + DS1000, + DS2000, + DS2000A, + DSO1000, +}; + +/* short name, full name */ +static const struct rigol_ds_vendor supported_vendors[] = { + [RIGOL] = {"Rigol", "Rigol Technologies"}, + [AGILENT] = {"Agilent", "Rigol Technologies"}, +}; -#define RIGOL "Rigol Technologies" -#define AGILENT "Agilent Technologies" -#define RIGOL_SHORT "Rigol" -#define AGILENT_SHORT "Agilent" +#define VENDOR(x) &supported_vendors[x] +/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs, + * live waveform samples, memory buffer samples */ +static const struct rigol_ds_series supported_series[] = { + [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW, + {50, 1}, {2, 1000}, 14, 2048, 0}, + [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2, + {50, 1}, {2, 1000}, 12, 600, 1048576}, + [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2, + {500, 1}, {2, 1000}, 14, 1400, 14000}, + [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2, + {1000, 1}, {500, 1000000}, 14, 1400, 14000}, + [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2, + {50, 1}, {2, 1000}, 12, 600, 20480}, +}; +#define SERIES(x) &supported_series[x] +/* series, model, min timebase, analog channels, digital */ static const struct rigol_ds_model supported_models[] = { - {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12}, - {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12}, - {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12}, - {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12}, - {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12}, - {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12}, - {RIGOL, "DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2302", RIGOL_DS2000, PROTOCOL_IEEE488_2, {1, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2072A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2102A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2202A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "DS2302A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {1, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14}, - {RIGOL, "VS5022", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14}, - {RIGOL, "VS5022D", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14}, - {RIGOL, "VS5042", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14}, - {RIGOL, "VS5042D", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14}, - {RIGOL, "VS5062", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14}, - {RIGOL, "VS5062D", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14}, - {RIGOL, "VS5102", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14}, - {RIGOL, "VS5102D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14}, - {RIGOL, "VS5202", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14}, - {RIGOL, "VS5202D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14}, - {AGILENT, "DSO1002A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12}, - {AGILENT, "DSO1004A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12}, - {AGILENT, "DSO1012A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12}, - {AGILENT, "DSO1014A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12}, - {AGILENT, "DSO1022A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12}, - {AGILENT, "DSO1024A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12}, + {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false}, + {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false}, + {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false}, + {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false}, + {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false}, + {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true}, + {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true}, + {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true}, + {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true}, + {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true}, + {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false}, + {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false}, + {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false}, + {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true}, + {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true}, + {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true}, + {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false}, + {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false}, + {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false}, + {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false}, + {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false}, + {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false}, + {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false}, + {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false}, + {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false}, + {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false}, + {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false}, + {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false}, + {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false}, + {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false}, }; SR_PRIV struct sr_dev_driver rigol_ds_driver_info; @@ -223,21 +250,6 @@ static int dev_clear(void) return std_dev_clear(di, clear_helper); } -static int set_cfg(const struct sr_dev_inst *sdi, const char *format, ...) -{ - va_list args; - int ret; - - va_start(args, format); - ret = sr_scpi_send_variadic(sdi->conn, format, args); - va_end(args); - - if (ret != SR_OK) - return SR_ERR; - - return sr_scpi_get_opc(sdi->conn); -} - static int init(struct sr_context *sr_ctx) { return std_init(sr_ctx, di, LOG_PREFIX); @@ -250,9 +262,10 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev struct sr_scpi_dev_inst *scpi; struct sr_scpi_hw_info *hw_info; struct sr_probe *probe; + long n[3]; unsigned int i; const struct rigol_ds_model *model = NULL; - gchar *channel_name, *vendor; + gchar *channel_name, **version; *devices = NULL; @@ -273,21 +286,17 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev } for (i = 0; i < ARRAY_SIZE(supported_models); i++) { - if (!strcasecmp(hw_info->manufacturer, supported_models[i].vendor) && + if (!strcasecmp(hw_info->manufacturer, + supported_models[i].series->vendor->full_name) && !strcmp(hw_info->model, supported_models[i].name)) { model = &supported_models[i]; break; } } - if (!strcmp(hw_info->manufacturer, RIGOL)) - vendor = RIGOL_SHORT; - else if (!strcmp(hw_info->manufacturer, AGILENT)) - vendor = AGILENT_SHORT; - else - vendor = hw_info->manufacturer; if (!model || !(sdi = sr_dev_inst_new(0, SR_ST_ACTIVE, - vendor, hw_info->model, + model->series->vendor->name, + model->name, hw_info->firmware_version))) { sr_scpi_hw_info_free(hw_info); sr_scpi_close(scpi); @@ -295,7 +304,6 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev return SR_ERR_NA; } - sr_scpi_hw_info_free(hw_info); sr_scpi_close(scpi); sdi->conn = scpi; @@ -308,6 +316,33 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev devc->limit_frames = 0; devc->model = model; + devc->format = model->series->format; + + /* DS1000 models with firmware before 0.2.4 used the old data format. */ + if (model->series == SERIES(DS1000)) { + version = g_strsplit(hw_info->firmware_version, ".", 0); + do { + if (!version[0] || !version[1] || !version[2]) + break; + if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0) + break; + for (i = 0; i < 3; i++) { + if (sr_atol(version[i], &n[i]) != SR_OK) + break; + } + if (i != 3) + break; + if (n[0] != 0 || n[1] > 2) + break; + if (n[1] == 2 && n[2] > 3) + break; + sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format."); + devc->format = FORMAT_RAW; + } while(0); + g_strfreev(version); + } + + sr_scpi_hw_info_free(hw_info); for (i = 0; i < model->analog_channels; i++) { if (!(channel_name = g_strdup_printf("CH%d", i + 1))) @@ -340,12 +375,12 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev for (i = 0; i < NUM_TIMEBASE; i++) { if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2]))) devc->timebases = &timebases[i]; - if (!memcmp(&devc->model->max_timebase, &timebases[i], sizeof(uint64_t[2]))) + if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2]))) devc->num_timebases = &timebases[i] - devc->timebases + 1; } for (i = 0; i < NUM_VDIV; i++) - if (!memcmp(&devc->model->min_vdiv, &vdivs[i], sizeof(uint64_t[2]))) + if (!memcmp(&devc->model->series->min_vdiv, &vdivs[i], sizeof(uint64_t[2]))) devc->vdivs = &vdivs[i]; if (!(devc->buffer = g_try_malloc(ACQ_BUFFER_SIZE))) @@ -445,8 +480,13 @@ static int dev_open(struct sr_dev_inst *sdi) static int dev_close(struct sr_dev_inst *sdi) { struct sr_scpi_dev_inst *scpi; + struct dev_context *devc; scpi = sdi->conn; + devc = sdi->priv; + + if (devc->model->series->protocol >= PROTOCOL_V2) + rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE"); if (scpi) { if (sr_scpi_close(scpi) < 0) @@ -469,28 +509,22 @@ static int analog_frame_size(const struct sr_dev_inst *sdi) int analog_probes = 0; GSList *l; - switch (devc->model->series) { - case RIGOL_VS5000: - return VS5000_ANALOG_LIVE_WAVEFORM_SIZE; - case RIGOL_DS1000: - return DS1000_ANALOG_LIVE_WAVEFORM_SIZE; + for (l = sdi->probes; l; l = l->next) { + probe = l->data; + if (probe->type == SR_PROBE_ANALOG && probe->enabled) + analog_probes++; + } + + if (analog_probes == 0) + return 0; + + switch (devc->data_source) { + case DATA_SOURCE_LIVE: + return devc->model->series->live_samples; + case DATA_SOURCE_MEMORY: + return devc->model->series->buffer_samples / analog_probes; default: - for (l = sdi->probes; l; l = l->next) { - probe = l->data; - if (probe->type == SR_PROBE_ANALOG && probe->enabled) - analog_probes++; - } - if (devc->data_source == DATA_SOURCE_MEMORY) { - if (analog_probes == 1) - return DS2000_ANALOG_MEM_WAVEFORM_SIZE_1C; - else - return DS2000_ANALOG_MEM_WAVEFORM_SIZE_2C; - } else { - if (devc->model->series == AGILENT_DSO1000) - return DSO1000_ANALOG_LIVE_WAVEFORM_SIZE; - else - return DS2000_ANALOG_LIVE_WAVEFORM_SIZE; - } + return 0; } } @@ -498,11 +532,11 @@ static int digital_frame_size(const struct sr_dev_inst *sdi) { struct dev_context *devc = sdi->priv; - switch (devc->model->series) { - case RIGOL_VS5000: - return VS5000_DIGITAL_WAVEFORM_SIZE; - case RIGOL_DS1000: - return DS1000_DIGITAL_WAVEFORM_SIZE; + switch (devc->data_source) { + case DATA_SOURCE_LIVE: + return devc->model->series->live_samples * 2; + case DATA_SOURCE_MEMORY: + return devc->model->series->buffer_samples * 2; default: return 0; } @@ -542,7 +576,7 @@ static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, switch (id) { case SR_CONF_NUM_TIMEBASE: - *data = g_variant_new_int32(devc->model->num_horizontal_divs); + *data = g_variant_new_int32(devc->model->series->num_horizontal_divs); break; case SR_CONF_NUM_VDIV: *data = g_variant_new_int32(NUM_VDIV); @@ -557,7 +591,7 @@ static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, case SR_CONF_SAMPLERATE: if (devc->data_source == DATA_SOURCE_LIVE) { samplerate = analog_frame_size(sdi) / - (devc->timebase * devc->model->num_horizontal_divs); + (devc->timebase * devc->model->series->num_horizontal_divs); *data = g_variant_new_uint64(samplerate); } else { return SR_ERR_NA; @@ -653,7 +687,7 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, return SR_ERR; g_free(devc->trigger_slope); devc->trigger_slope = g_strdup(tmp_u64 ? "POS" : "NEG"); - ret = set_cfg(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope); + ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope); break; case SR_CONF_HORIZ_TRIGGERPOS: t_dbl = g_variant_get_double(data); @@ -664,7 +698,7 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, * need to express this in seconds. */ t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases; g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl); - ret = set_cfg(sdi, ":TIM:OFFS %s", buffer); + ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer); break; case SR_CONF_TIMEBASE: g_variant_get(data, "(tt)", &p, &q); @@ -673,7 +707,7 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, devc->timebase = (float)p / q; g_ascii_formatd(buffer, sizeof(buffer), "%.9f", devc->timebase); - ret = set_cfg(sdi, ":TIM:SCAL %s", buffer); + ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer); break; } } @@ -698,7 +732,7 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, tmp_str = "CHAN4"; else tmp_str = (char *)devc->trigger_source; - ret = set_cfg(sdi, ":TRIG:EDGE:SOUR %s", tmp_str); + ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str); break; } } @@ -719,7 +753,7 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, devc->vdiv[i] = (float)p / q; g_ascii_formatd(buffer, sizeof(buffer), "%.3f", devc->vdiv[i]); - return set_cfg(sdi, ":CHAN%d:SCAL %s", i + 1, + return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1, buffer); } return SR_ERR_ARG; @@ -738,7 +772,7 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, if (!strcmp(tmp_str, coupling[j])) { g_free(devc->coupling[i]); devc->coupling[i] = g_strdup(coupling[j]); - return set_cfg(sdi, ":CHAN%d:COUP %s", i + 1, + return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1, devc->coupling[i]); } } @@ -750,9 +784,10 @@ static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, tmp_str = g_variant_get_string(data, NULL); if (!strcmp(tmp_str, "Live")) devc->data_source = DATA_SOURCE_LIVE; - else if (!strcmp(tmp_str, "Memory")) + else if (devc->model->series->protocol >= PROTOCOL_V2 + && !strcmp(tmp_str, "Memory")) devc->data_source = DATA_SOURCE_MEMORY; - else if (devc->model->series >= RIGOL_DS1000Z + else if (devc->model->series->protocol >= PROTOCOL_V3 && !strcmp(tmp_str, "Segmented")) devc->data_source = DATA_SOURCE_SEGMENTED; else @@ -871,11 +906,17 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, if (!devc) /* Can't know this until we have the exact model. */ return SR_ERR_ARG; - /* This needs tweaking by series/model! */ - if (devc->model->series == RIGOL_DS2000) - *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources)); - else + switch (devc->model->series->protocol) { + case PROTOCOL_V1: + *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2); + break; + case PROTOCOL_V2: *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1); + break; + default: + *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources)); + break; + } break; default: return SR_ERR_NA; @@ -909,7 +950,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) devc->enabled_analog_probes, probe); if (probe->enabled != devc->analog_channels[probe->index]) { /* Enabled channel is currently disabled, or vice versa. */ - if (set_cfg(sdi, ":CHAN%d:DISP %s", probe->index + 1, + if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", probe->index + 1, probe->enabled ? "ON" : "OFF") != SR_OK) return SR_ERR; devc->analog_channels[probe->index] = probe->enabled; @@ -920,14 +961,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) devc->enabled_digital_probes, probe); /* Turn on LA module if currently off. */ if (!devc->la_enabled) { - if (set_cfg(sdi, ":LA:DISP ON") != SR_OK) + if (rigol_ds_config_set(sdi, ":LA:DISP ON") != SR_OK) return SR_ERR; devc->la_enabled = TRUE; } } if (probe->enabled != devc->digital_channels[probe->index]) { /* Enabled channel is currently disabled, or vice versa. */ - if (set_cfg(sdi, ":DIG%d:TURN %s", probe->index, + if (rigol_ds_config_set(sdi, ":DIG%d:TURN %s", probe->index, probe->enabled ? "ON" : "OFF") != SR_OK) return SR_ERR; devc->digital_channels[probe->index] = probe->enabled; @@ -940,22 +981,43 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) /* Turn off LA module if on and no digital probes selected. */ if (devc->la_enabled && !devc->enabled_digital_probes) - if (set_cfg(sdi, ":LA:DISP OFF") != SR_OK) + if (rigol_ds_config_set(sdi, ":LA:DISP OFF") != SR_OK) return SR_ERR; - if (devc->data_source == DATA_SOURCE_LIVE) { - if (set_cfg(sdi, ":RUN") != SR_OK) - return SR_ERR; - } else if (devc->data_source == DATA_SOURCE_MEMORY) { - if (devc->model->series != RIGOL_DS2000) { - sr_err("Data source 'Memory' not supported for this device"); - return SR_ERR; - } - } else if (devc->data_source == DATA_SOURCE_SEGMENTED) { + /* Set memory mode. */ + if (devc->data_source == DATA_SOURCE_SEGMENTED) { sr_err("Data source 'Segmented' not yet supported"); return SR_ERR; } + devc->analog_frame_size = analog_frame_size(sdi); + devc->digital_frame_size = digital_frame_size(sdi); + + switch (devc->model->series->protocol) { + case PROTOCOL_V2: + if (rigol_ds_config_set(sdi, ":ACQ:MDEP LONG") != SR_OK) + return SR_ERR; + break; + case PROTOCOL_V3: + /* Apparently for the DS2000 the memory + * depth can only be set in Running state - + * this matches the behaviour of the UI. */ + if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) + return SR_ERR; + if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d", + devc->analog_frame_size) != SR_OK) + return SR_ERR; + if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) + return SR_ERR; + break; + default: + break; + } + + if (devc->data_source == DATA_SOURCE_LIVE) + if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) + return SR_ERR; + sr_scpi_source_add(scpi, G_IO_IN, 50, rigol_ds_receive, (void *)sdi); /* Send header packet to the session bus. */ @@ -966,30 +1028,8 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) else devc->channel_entry = devc->enabled_digital_probes; - devc->analog_frame_size = analog_frame_size(sdi); - devc->digital_frame_size = digital_frame_size(sdi); - - if (devc->model->series < RIGOL_DS1000Z) { - /* Fetch the first frame. */ - if (rigol_ds_channel_start(sdi) != SR_OK) - return SR_ERR; - } else { - if (devc->enabled_analog_probes) { - if (devc->data_source == DATA_SOURCE_MEMORY) { - /* Apparently for the DS2000 the memory - * depth can only be set in Running state - - * this matches the behaviour of the UI. */ - if (set_cfg(sdi, ":RUN") != SR_OK) - return SR_ERR; - if (set_cfg(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK) - return SR_ERR; - if (set_cfg(sdi, ":STOP") != SR_OK) - return SR_ERR; - } - if (rigol_ds_capture_start(sdi) != SR_OK) - return SR_ERR; - } - } + if (rigol_ds_capture_start(sdi) != SR_OK) + return SR_ERR; /* Start of first frame. */ packet.type = SR_DF_FRAME_BEGIN;