X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=hardware%2Flink-mso19%2Flink-mso19.h;h=53112bef320081aa43ea3794c81b875c8d1bdca6;hb=40dda2c3a509e9e031078427e32249e2ebc33ec5;hp=f88ee723c536976948330ad19c3187ccc5c1d834;hpb=80aa5f23d1225776a7db0fc6faa763bb5c141dcf;p=libsigrok.git

diff --git a/hardware/link-mso19/link-mso19.h b/hardware/link-mso19/link-mso19.h
index f88ee723..53112bef 100644
--- a/hardware/link-mso19/link-mso19.h
+++ b/hardware/link-mso19/link-mso19.h
@@ -18,8 +18,8 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef SIGROK_LINK_MSO19_H
-#define SIGROK_LINK_MSO19_H
+#ifndef LIBSIGROK_HARDWARE_LINK_MSO19_LINK_MSO19_H
+#define LIBSIGROK_HARDWARE_LINK_MSO19_LINK_MSO19_H
 
 /* Structure for the pattern generator state */
 struct mso_patgen {
@@ -51,7 +51,7 @@ struct mso_prototrig {
 	uint8_t spimode;
 };
 
-/* our private per-instance data */
+/* Private, per-device-instance driver context. */
 struct mso {
 	/* info */
 	uint8_t hwmodel;
@@ -63,22 +63,22 @@ struct mso {
 	uint16_t dac_offset;
 	uint16_t offset_range;
 	/* register cache */
-	uint8_t ctlbase;
-	uint8_t slowmode;
+	uint8_t ctlbase1;
+	uint8_t ctlbase2;
 	/* state */
 	uint8_t la_threshold;
 	uint64_t cur_rate;
 	uint8_t dso_probe_attn;
 	uint8_t trigger_chan;
 	uint8_t trigger_slope;
-	uint8_t trigger_spimode;
 	uint8_t trigger_outsrc;
 	uint8_t trigger_state;
 	uint8_t la_trigger;
 	uint8_t la_trigger_mask;
 	double dso_trigger_voltage;
 	uint16_t dso_trigger_width;
-	gpointer session_id;
+	struct mso_prototrig protocol_trigger;
+	void *session_dev_id;
 	uint16_t buffer_n;
 	char buffer[4096];
 };
@@ -91,21 +91,34 @@ struct mso {
 const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
 const char mso_foot[] = { 0x7e };
 
-/* registers */
+/* bank agnostic registers */
+#define REG_CTL2		15
+
+/* bank 0 registers */
 #define REG_BUFFER		1
 #define REG_TRIGGER		2
 #define REG_CLKRATE1		9
 #define REG_CLKRATE2		10
 #define REG_DAC1		12
 #define REG_DAC2		13
-#define REG_CTL			14
+/* possibly bank agnostic: */
+#define REG_CTL1		14
+
+/* bank 2 registers (SPI/I2C protocol trigger) */
+#define REG_PT_WORD(x)	       (x)
+#define REG_PT_MASK(x)	       (x+4)
+#define REG_PT_SPIMODE          8
+
+/* bits - REG_CTL1 */
+#define BIT_CTL1_RESETFSM      (1 << 0)
+#define BIT_CTL1_ARM	       (1 << 1)
+#define BIT_CTL1_ADC_UNKNOWN4  (1 << 4) /* adc enable? */
+#define BIT_CTL1_RESETADC      (1 << 6)
+#define BIT_CTL1_LED	       (1 << 7)
 
-/* bits */
-#define BIT_CTL_RESETFSM	(1 << 0)
-#define BIT_CTL_ARM		(1 << 1)
-#define BIT_CTL_ADC_UNKNOWN4	(1 << 4) /* adc enable? */
-#define BIT_CTL_RESETADC	(1 << 6)
-#define BIT_CTL_LED		(1 << 7)
+/* bits - REG_CTL2 */
+#define BITS_CTL2_BANK(x)      (x & 0x3)
+#define BIT_CTL2_SLOWMODE      (1 << 5)
 
 struct rate_map {
 	uint32_t rate;
@@ -137,7 +150,7 @@ static struct rate_map rate_map[] = {
 };
 
 /* FIXME: Determine corresponding voltages */
-uint16_t la_threshold_map[] = {
+static uint16_t la_threshold_map[] = {
 	0x8600,
 	0x8770,
 	0x88ff,