X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=hardware%2Fasix-sigma%2Fasix-sigma.c;h=39e2dbed79cb8ef364557173c0a6b7a96abb436b;hb=46641facd4ad8de4a93910d7089c7b289b412443;hp=cc77a647a08ac110b2a25497adf17ac76f531bf7;hpb=eec5275e2f3dfa1b9bb51a1b054dc7d8bd3bac20;p=libsigrok.git

diff --git a/hardware/asix-sigma/asix-sigma.c b/hardware/asix-sigma/asix-sigma.c
index cc77a647..59acdcb1 100644
--- a/hardware/asix-sigma/asix-sigma.c
+++ b/hardware/asix-sigma/asix-sigma.c
@@ -1,7 +1,7 @@
 /*
- * This file is part of the sigrok project.
+ * This file is part of the libsigrok project.
  *
- * Copyright (C) 2010 HÃ¥vard Espeland <gus@ping.uio.no>,
+ * Copyright (C) 2010-2012 HÃ¥vard Espeland <gus@ping.uio.no>,
  * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
  * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
  *
@@ -20,13 +20,15 @@
  */
 
 /*
- * ASIX Sigma Logic Analyzer Driver
+ * ASIX SIGMA/SIGMA2 logic analyzer driver
  */
 
+#include <glib.h>
+#include <glib/gstdio.h>
 #include <ftdi.h>
 #include <string.h>
-#include <zlib.h>
-#include <sigrok.h>
+#include "libsigrok.h"
+#include "libsigrok-internal.h"
 #include "asix-sigma.h"
 
 #define USB_VENDOR			0xa600
@@ -34,109 +36,93 @@
 #define USB_DESCRIPTION			"ASIX SIGMA"
 #define USB_VENDOR_NAME			"ASIX"
 #define USB_MODEL_NAME			"SIGMA"
-#define USB_MODEL_VERSION		""
-#define TRIGGER_TYPES			"rf"
-
-static GSList *device_instances = NULL;
-
-// XXX These should be per device
-static struct ftdi_context ftdic;
-static uint64_t cur_samplerate = 0;
-static uint32_t limit_msec = 0;
-static struct timeval start_tv;
-static int cur_firmware = -1;
-static int num_probes = 0;
-static int samples_per_event = 0;
-static int capture_ratio = 50;
-
-/* Single-pin trigger support. */
-static uint8_t triggerpin = 1;
-static uint8_t triggerfall = 0;
-
-static uint64_t supported_samplerates[] = {
-	KHZ(200),
-	KHZ(250),
-	KHZ(500),
-	MHZ(1),
-	MHZ(5),
-	MHZ(10),
-	MHZ(25),
-	MHZ(50),
-	MHZ(100),
-	MHZ(200),
-	0,
-};
-
-static struct samplerates samplerates = {
-	KHZ(200),
-	MHZ(200),
-	0,
-	supported_samplerates,
-};
-
-static int capabilities[] = {
-	HWCAP_LOGIC_ANALYZER,
-	HWCAP_SAMPLERATE,
-	HWCAP_CAPTURE_RATIO,
-	HWCAP_PROBECONFIG,
+#define TRIGGER_TYPE 			"rf10"
 
-	HWCAP_LIMIT_MSEC,
-	0,
-};
+SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
+static struct sr_dev_driver *di = &asix_sigma_driver_info;
+static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
 
-/* Force the FPGA to reboot. */
-static uint8_t suicide[] = {
-	0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
+/*
+ * The ASIX Sigma supports arbitrary integer frequency divider in
+ * the 50MHz mode. The divider is in range 1...256 , allowing for
+ * very precise sampling rate selection. This driver supports only
+ * a subset of the sampling rates.
+ */
+static const uint64_t samplerates[] = {
+	SR_KHZ(200),	/* div=250 */
+	SR_KHZ(250),	/* div=200 */
+	SR_KHZ(500),	/* div=100 */
+	SR_MHZ(1),	/* div=50  */
+	SR_MHZ(5),	/* div=10  */
+	SR_MHZ(10),	/* div=5   */
+	SR_MHZ(25),	/* div=2   */
+	SR_MHZ(50),	/* div=1   */
+	SR_MHZ(100),	/* Special FW needed */
+	SR_MHZ(200),	/* Special FW needed */
 };
 
-/* Prepare to upload firmware (FPGA specific). */
-static uint8_t init[] = {
-	0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+/*
+ * Channel numbers seem to go from 1-16, according to this image:
+ * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
+ * (the cable has two additional GND pins, and a TI and TO pin)
+ */
+static const char *channel_names[] = {
+	"1", "2", "3", "4", "5", "6", "7", "8",
+	"9", "10", "11", "12", "13", "14", "15", "16",
 };
 
-/* Initialize the logic analyzer mode. */
-static uint8_t logic_mode_start[] = {
-	0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
-	0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
+static const int32_t hwcaps[] = {
+	SR_CONF_LOGIC_ANALYZER,
+	SR_CONF_SAMPLERATE,
+	SR_CONF_TRIGGER_TYPE,
+	SR_CONF_CAPTURE_RATIO,
+	SR_CONF_LIMIT_MSEC,
+	SR_CONF_LIMIT_SAMPLES,
 };
 
-static const char *firmware_files[] = {
-	"asix-sigma-50.fw",	/* 50 MHz, supports 8 bit fractions */
-	"asix-sigma-100.fw",	/* 100 MHz */
-	"asix-sigma-200.fw",	/* 200 MHz */
-	"asix-sigma-50sync.fw",	/* Synchronous clock from pin */
-	"asix-sigma-phasor.fw",	/* Frequency counter */
+static const char *sigma_firmware_files[] = {
+	/* 50 MHz, supports 8 bit fractions */
+	FIRMWARE_DIR "/asix-sigma-50.fw",
+	/* 100 MHz */
+	FIRMWARE_DIR "/asix-sigma-100.fw",
+	/* 200 MHz */
+	FIRMWARE_DIR "/asix-sigma-200.fw",
+	/* Synchronous clock from pin */
+	FIRMWARE_DIR "/asix-sigma-50sync.fw",
+	/* Frequency counter */
+	FIRMWARE_DIR "/asix-sigma-phasor.fw",
 };
 
-static int sigma_read(void *buf, size_t size)
+static int sigma_read(void *buf, size_t size, struct dev_context *devc)
 {
 	int ret;
 
-	ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
+	ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
 	if (ret < 0) {
-		g_warning("ftdi_read_data failed: %s",
-			  ftdi_get_error_string(&ftdic));
+		sr_err("ftdi_read_data failed: %s",
+		       ftdi_get_error_string(&devc->ftdic));
 	}
 
 	return ret;
 }
 
-static int sigma_write(void *buf, size_t size)
+static int sigma_write(void *buf, size_t size, struct dev_context *devc)
 {
 	int ret;
 
-	ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
+	ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
 	if (ret < 0) {
-		g_warning("ftdi_write_data failed: %s",
-			  ftdi_get_error_string(&ftdic));
+		sr_err("ftdi_write_data failed: %s",
+		       ftdi_get_error_string(&devc->ftdic));
 	} else if ((size_t) ret != size) {
-		g_warning("ftdi_write_data did not complete write\n");
+		sr_err("ftdi_write_data did not complete write.");
 	}
 
 	return ret;
 }
 
-static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
+static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
+				struct dev_context *devc)
 {
 	size_t i;
 	uint8_t buf[len + 2];
@@ -150,15 +136,16 @@ static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
 		buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
 	}
 
-	return sigma_write(buf, idx);
+	return sigma_write(buf, idx, devc);
 }
 
-static int sigma_set_register(uint8_t reg, uint8_t value)
+static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
 {
-	return sigma_write_register(reg, &value, 1);
+	return sigma_write_register(reg, &value, 1, devc);
 }
 
-static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
+static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
+			       struct dev_context *devc)
 {
 	uint8_t buf[3];
 
@@ -166,24 +153,25 @@ static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
 	buf[1] = REG_ADDR_HIGH | (reg >> 4);
 	buf[2] = REG_READ_ADDR;
 
-	sigma_write(buf, sizeof(buf));
+	sigma_write(buf, sizeof(buf), devc);
 
-	return sigma_read(data, len);
+	return sigma_read(data, len, devc);
 }
 
-static uint8_t sigma_get_register(uint8_t reg)
+static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
 {
 	uint8_t value;
 
-	if (1 != sigma_read_register(reg, &value, 1)) {
-		g_warning("Sigma_get_register: 1 byte expected");
+	if (1 != sigma_read_register(reg, &value, 1, devc)) {
+		sr_err("sigma_get_register: 1 byte expected");
 		return 0;
 	}
 
 	return value;
 }
 
-static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
+static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
+			  struct dev_context *devc)
 {
 	uint8_t buf[] = {
 		REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
@@ -197,9 +185,9 @@ static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
 	};
 	uint8_t result[6];
 
-	sigma_write(buf, sizeof(buf));
+	sigma_write(buf, sizeof(buf), devc);
 
-	sigma_read(result, sizeof(result));
+	sigma_read(result, sizeof(result), devc);
 
 	*triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
 	*stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
@@ -214,7 +202,8 @@ static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
 	return 1;
 }
 
-static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
+static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
+			   uint8_t *data, struct dev_context *devc)
 {
 	size_t i;
 	uint8_t buf[4096];
@@ -223,7 +212,7 @@ static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
 	/* Send the startchunk. Index start with 1. */
 	buf[0] = startchunk >> 8;
 	buf[1] = startchunk & 0xff;
-	sigma_write_register(WRITE_MEMROW, buf, 2);
+	sigma_write_register(WRITE_MEMROW, buf, 2, devc);
 
 	/* Read the DRAM. */
 	buf[idx++] = REG_DRAM_BLOCK;
@@ -240,395 +229,713 @@ static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
 			buf[idx++] = REG_DRAM_WAIT_ACK;
 	}
 
-	sigma_write(buf, idx);
+	sigma_write(buf, idx, devc);
 
-	return sigma_read(data, numchunks * CHUNK_SIZE);
+	return sigma_read(data, numchunks * CHUNK_SIZE, devc);
 }
 
-/* Generate the bitbang stream for programming the FPGA. */
-static int bin2bitbang(const char *filename,
-		       unsigned char **buf, size_t *buf_size)
+/* Upload trigger look-up tables to Sigma. */
+static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
 {
-	FILE *f;
-	long file_size;
-	unsigned long offset = 0;
-	unsigned char *p;
-	uint8_t *compressed_buf, *firmware;
-	uLongf csize, fwsize;
-	const int buffer_size = 65536;
-	size_t i;
-	int c, ret, bit, v;
-	uint32_t imm = 0x3f6df2ab;
-
-	f = fopen(filename, "r");
-	if (!f) {
-		g_warning("fopen(\"%s\", \"r\")", filename);
-		return -1;
+	int i;
+	uint8_t tmp[2];
+	uint16_t bit;
+
+	/* Transpose the table and send to Sigma. */
+	for (i = 0; i < 16; ++i) {
+		bit = 1 << i;
+
+		tmp[0] = tmp[1] = 0;
+
+		if (lut->m2d[0] & bit)
+			tmp[0] |= 0x01;
+		if (lut->m2d[1] & bit)
+			tmp[0] |= 0x02;
+		if (lut->m2d[2] & bit)
+			tmp[0] |= 0x04;
+		if (lut->m2d[3] & bit)
+			tmp[0] |= 0x08;
+
+		if (lut->m3 & bit)
+			tmp[0] |= 0x10;
+		if (lut->m3s & bit)
+			tmp[0] |= 0x20;
+		if (lut->m4 & bit)
+			tmp[0] |= 0x40;
+
+		if (lut->m0d[0] & bit)
+			tmp[1] |= 0x01;
+		if (lut->m0d[1] & bit)
+			tmp[1] |= 0x02;
+		if (lut->m0d[2] & bit)
+			tmp[1] |= 0x04;
+		if (lut->m0d[3] & bit)
+			tmp[1] |= 0x08;
+
+		if (lut->m1d[0] & bit)
+			tmp[1] |= 0x10;
+		if (lut->m1d[1] & bit)
+			tmp[1] |= 0x20;
+		if (lut->m1d[2] & bit)
+			tmp[1] |= 0x40;
+		if (lut->m1d[3] & bit)
+			tmp[1] |= 0x80;
+
+		sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
+				     devc);
+		sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
 	}
 
-	if (-1 == fseek(f, 0, SEEK_END)) {
-		g_warning("fseek on %s failed", filename);
-		fclose(f);
-		return -1;
-	}
+	/* Send the parameters */
+	sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
+			     sizeof(lut->params), devc);
 
-	file_size = ftell(f);
+	return SR_OK;
+}
 
-	fseek(f, 0, SEEK_SET);
+static void clear_helper(void *priv)
+{
+	struct dev_context *devc;
 
-	compressed_buf = g_malloc(file_size);
-	firmware = g_malloc(buffer_size);
+	devc = priv;
 
-	if (!compressed_buf || !firmware) {
-		g_warning("Error allocating buffers");
-		return -1;
-	}
+	ftdi_deinit(&devc->ftdic);
+}
 
-	csize = 0;
-	while ((c = getc(f)) != EOF) {
-		imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
-		compressed_buf[csize++] = c ^ imm;
-	}
-	fclose(f);
+static int dev_clear(void)
+{
+	return std_dev_clear(di, clear_helper);
+}
 
-	fwsize = buffer_size;
-	ret = uncompress(firmware, &fwsize, compressed_buf, csize);
-	if (ret < 0) {
-		g_free(compressed_buf);
-		g_free(firmware);
-		g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
-		return -1;
+static int init(struct sr_context *sr_ctx)
+{
+	return std_init(sr_ctx, di, LOG_PREFIX);
+}
+
+static GSList *scan(GSList *options)
+{
+	struct sr_dev_inst *sdi;
+	struct sr_channel *ch;
+	struct drv_context *drvc;
+	struct dev_context *devc;
+	GSList *devices;
+	struct ftdi_device_list *devlist;
+	char serial_txt[10];
+	uint32_t serial;
+	int ret;
+	unsigned int i;
+
+	(void)options;
+
+	drvc = di->priv;
+
+	devices = NULL;
+
+	if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
+		sr_err("%s: devc malloc failed", __func__);
+		return NULL;
 	}
 
-	g_free(compressed_buf);
+	ftdi_init(&devc->ftdic);
+
+	/* Look for SIGMAs. */
 
-	*buf_size = fwsize * 2 * 8;
+	if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
+	    USB_VENDOR, USB_PRODUCT)) <= 0) {
+		if (ret < 0)
+			sr_err("ftdi_usb_find_all(): %d", ret);
+		goto free;
+	}
 
-	*buf = p = (unsigned char *)g_malloc(*buf_size);
+	/* Make sure it's a version 1 or 2 SIGMA. */
+	ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
+			     serial_txt, sizeof(serial_txt));
+	sscanf(serial_txt, "%x", &serial);
 
-	if (!p) {
-		g_warning("Error allocating buffers");
-		return -1;
+	if (serial < 0xa6010000 || serial > 0xa602ffff) {
+		sr_err("Only SIGMA and SIGMA2 are supported "
+		       "in this version of libsigrok.");
+		goto free;
 	}
 
-	for (i = 0; i < fwsize; ++i) {
-		for (bit = 7; bit >= 0; --bit) {
-			v = firmware[i] & 1 << bit ? 0x40 : 0x00;
-			p[offset++] = v | 0x01;
-			p[offset++] = v;
-		}
+	sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
+
+	devc->cur_samplerate = 0;
+	devc->period_ps = 0;
+	devc->limit_msec = 0;
+	devc->cur_firmware = -1;
+	devc->num_channels = 0;
+	devc->samples_per_event = 0;
+	devc->capture_ratio = 50;
+	devc->use_triggers = 0;
+
+	/* Register SIGMA device. */
+	if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
+				    USB_MODEL_NAME, NULL))) {
+		sr_err("%s: sdi was NULL", __func__);
+		goto free;
 	}
+	sdi->driver = di;
+
+	for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
+		ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
+				    channel_names[i]);
+		if (!ch)
+			return NULL;
+		sdi->channels = g_slist_append(sdi->channels, ch);
+	}
+
+	devices = g_slist_append(devices, sdi);
+	drvc->instances = g_slist_append(drvc->instances, sdi);
+	sdi->priv = devc;
 
-	g_free(firmware);
+	/* We will open the device again when we need it. */
+	ftdi_list_free(&devlist);
+
+	return devices;
+
+free:
+	ftdi_deinit(&devc->ftdic);
+	g_free(devc);
+	return NULL;
+}
 
-	if (offset != *buf_size) {
-		g_free(*buf);
-		g_warning("Error reading firmware %s "
-			  "offset=%ld, file_size=%ld, buf_size=%zd\n",
-			  filename, offset, file_size, *buf_size);
+static GSList *dev_list(void)
+{
+	return ((struct drv_context *)(di->priv))->instances;
+}
 
-		return -1;
+/*
+ * Configure the FPGA for bitbang mode.
+ * This sequence is documented in section 2. of the ASIX Sigma programming
+ * manual. This sequence is necessary to configure the FPGA in the Sigma
+ * into Bitbang mode, in which it can be programmed with the firmware.
+ */
+static int sigma_fpga_init_bitbang(struct dev_context *devc)
+{
+	uint8_t suicide[] = {
+		0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
+	};
+	uint8_t init_array[] = {
+		0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
+		0x01, 0x01,
+	};
+	int i, ret, timeout = 10000;
+	uint8_t data;
+
+	/* Section 2. part 1), do the FPGA suicide. */
+	sigma_write(suicide, sizeof(suicide), devc);
+	sigma_write(suicide, sizeof(suicide), devc);
+	sigma_write(suicide, sizeof(suicide), devc);
+	sigma_write(suicide, sizeof(suicide), devc);
+
+	/* Section 2. part 2), do pulse on D1. */
+	sigma_write(init_array, sizeof(init_array), devc);
+	ftdi_usb_purge_buffers(&devc->ftdic);
+
+	/* Wait until the FPGA asserts D6/INIT_B. */
+	for (i = 0; i < timeout; i++) {
+		ret = sigma_read(&data, 1, devc);
+		if (ret < 0)
+			return ret;
+		/* Test if pin D6 got asserted. */
+		if (data & (1 << 5))
+			return 0;
+		/* The D6 was not asserted yet, wait a bit. */
+		usleep(10000);
 	}
 
-	return 0;
+	return SR_ERR_TIMEOUT;
 }
 
-static int hw_init(char *deviceinfo)
+/*
+ * Configure the FPGA for logic-analyzer mode.
+ */
+static int sigma_fpga_init_la(struct dev_context *devc)
 {
-	struct sigrok_device_instance *sdi;
+	/* Initialize the logic analyzer mode. */
+	uint8_t logic_mode_start[] = {
+		REG_ADDR_LOW  | (READ_ID & 0xf),
+		REG_ADDR_HIGH | (READ_ID >> 8),
+		REG_READ_ADDR,	/* Read ID register. */
+
+		REG_ADDR_LOW | (WRITE_TEST & 0xf),
+		REG_DATA_LOW | 0x5,
+		REG_DATA_HIGH_WRITE | 0x5,
+		REG_READ_ADDR,	/* Read scratch register. */
+
+		REG_DATA_LOW | 0xa,
+		REG_DATA_HIGH_WRITE | 0xa,
+		REG_READ_ADDR,	/* Read scratch register. */
+
+		REG_ADDR_LOW | (WRITE_MODE & 0xf),
+		REG_DATA_LOW | 0x0,
+		REG_DATA_HIGH_WRITE | 0x8,
+	};
 
-	deviceinfo = deviceinfo;
+	uint8_t result[3];
+	int ret;
 
-	ftdi_init(&ftdic);
+	/* Initialize the logic analyzer mode. */
+	sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
 
-	/* Look for SIGMAs. */
-	if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
-			       USB_DESCRIPTION, NULL) < 0)
-		return 0;
+	/* Expect a 3 byte reply since we issued three READ requests. */
+	ret = sigma_read(result, 3, devc);
+	if (ret != 3)
+		goto err;
 
-	/* Register SIGMA device. */
-	sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
-			USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
-	if (!sdi)
-		return 0;
+	if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
+		goto err;
 
-	device_instances = g_slist_append(device_instances, sdi);
+	return SR_OK;
+err:
+	sr_err("Configuration failed. Invalid reply received.");
+	return SR_ERR;
+}
 
-	/* We will open the device again when we need it. */
-	ftdi_usb_close(&ftdic);
+/*
+ * Read the firmware from a file and transform it into a series of bitbang
+ * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
+ * by the caller of this function.
+ */
+static int sigma_fw_2_bitbang(const char *filename,
+			      uint8_t **bb_cmd, gsize *bb_cmd_size)
+{
+	GMappedFile *file;
+	GError *error;
+	gsize i, file_size, bb_size;
+	gchar *firmware;
+	uint8_t *bb_stream, *bbs;
+	uint32_t imm;
+	int bit, v;
+	int ret = SR_OK;
+
+	/*
+	 * Map the file and make the mapped buffer writable.
+	 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
+	 *       will be modified. It will not be modified until someone uses
+	 *       g_file_set_contents() on it.
+	 */
+	error = NULL;
+	file = g_mapped_file_new(filename, TRUE, &error);
+	g_assert_no_error(error);
+
+	file_size = g_mapped_file_get_length(file);
+	firmware = g_mapped_file_get_contents(file);
+	g_assert(firmware);
+
+	/* Weird magic transformation below, I have no idea what it does. */
+	imm = 0x3f6df2ab;
+	for (i = 0; i < file_size; i++) {
+		imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
+		firmware[i] ^= imm & 0xff;
+	}
 
-	return 1;
+	/*
+	 * Now that the firmware is "transformed", we will transcribe the
+	 * firmware blob into a sequence of toggles of the Dx wires. This
+	 * sequence will be fed directly into the Sigma, which must be in
+	 * the FPGA bitbang programming mode.
+	 */
+
+	/* Each bit of firmware is transcribed as two toggles of Dx wires. */
+	bb_size = file_size * 8 * 2;
+	bb_stream = (uint8_t *)g_try_malloc(bb_size);
+	if (!bb_stream) {
+		sr_err("%s: Failed to allocate bitbang stream", __func__);
+		ret = SR_ERR_MALLOC;
+		goto exit;
+	}
+
+	bbs = bb_stream;
+	for (i = 0; i < file_size; i++) {
+		for (bit = 7; bit >= 0; bit--) {
+			v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
+			*bbs++ = v | 0x01;
+			*bbs++ = v;
+		}
+	}
+
+	/* The transformation completed successfully, return the result. */
+	*bb_cmd = bb_stream;
+	*bb_cmd_size = bb_size;
+
+exit:
+	g_mapped_file_unref(file);
+	return ret;
 }
 
-static int upload_firmware(int firmware_idx)
+static int upload_firmware(int firmware_idx, struct dev_context *devc)
 {
 	int ret;
 	unsigned char *buf;
 	unsigned char pins;
 	size_t buf_size;
-	unsigned char result[32];
-	char firmware_path[128];
+	const char *firmware = sigma_firmware_files[firmware_idx];
+	struct ftdi_context *ftdic = &devc->ftdic;
 
 	/* Make sure it's an ASIX SIGMA. */
-	if ((ret = ftdi_usb_open_desc(&ftdic,
-		USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
-		g_warning("ftdi_usb_open failed: %s",
-			  ftdi_get_error_string(&ftdic));
+	ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
+				 USB_DESCRIPTION, NULL);
+	if (ret < 0) {
+		sr_err("ftdi_usb_open failed: %s",
+		       ftdi_get_error_string(ftdic));
 		return 0;
 	}
 
-	if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
-		g_warning("ftdi_set_bitmode failed: %s",
-			  ftdi_get_error_string(&ftdic));
+	ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
+	if (ret < 0) {
+		sr_err("ftdi_set_bitmode failed: %s",
+		       ftdi_get_error_string(ftdic));
 		return 0;
 	}
 
 	/* Four times the speed of sigmalogan - Works well. */
-	if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
-		g_warning("ftdi_set_baudrate failed: %s",
-			  ftdi_get_error_string(&ftdic));
+	ret = ftdi_set_baudrate(ftdic, 750000);
+	if (ret < 0) {
+		sr_err("ftdi_set_baudrate failed: %s",
+		       ftdi_get_error_string(ftdic));
 		return 0;
 	}
 
-	/* Force the FPGA to reboot. */
-	sigma_write(suicide, sizeof(suicide));
-	sigma_write(suicide, sizeof(suicide));
-	sigma_write(suicide, sizeof(suicide));
-	sigma_write(suicide, sizeof(suicide));
-
-	/* Prepare to upload firmware (FPGA specific). */
-	sigma_write(init, sizeof(init));
-
-	ftdi_usb_purge_buffers(&ftdic);
-
-	/* Wait until the FPGA asserts INIT_B. */
-	while (1) {
-		ret = sigma_read(result, 1);
-		if (result[0] & 0x20)
-			break;
-	}
+	/* Initialize the FPGA for firmware upload. */
+	ret = sigma_fpga_init_bitbang(devc);
+	if (ret)
+		return ret;
 
 	/* Prepare firmware. */
-	snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
-		 firmware_files[firmware_idx]);
-
-	if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
-		g_warning("An error occured while reading the firmware: %s",
-			  firmware_path);
-		return SIGROK_ERR;
+	ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
+	if (ret != SR_OK) {
+		sr_err("An error occured while reading the firmware: %s",
+		       firmware);
+		return ret;
 	}
 
 	/* Upload firmare. */
-	sigma_write(buf, buf_size);
+	sr_info("Uploading firmware file '%s'.", firmware);
+	sigma_write(buf, buf_size, devc);
 
 	g_free(buf);
 
-	if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
-		g_warning("ftdi_set_bitmode failed: %s",
-			  ftdi_get_error_string(&ftdic));
-		return SIGROK_ERR;
+	ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
+	if (ret < 0) {
+		sr_err("ftdi_set_bitmode failed: %s",
+		       ftdi_get_error_string(ftdic));
+		return SR_ERR;
 	}
 
-	ftdi_usb_purge_buffers(&ftdic);
+	ftdi_usb_purge_buffers(ftdic);
 
 	/* Discard garbage. */
-	while (1 == sigma_read(&pins, 1))
+	while (sigma_read(&pins, 1, devc) == 1)
 		;
 
-	/* Initialize the logic analyzer mode. */
-	sigma_write(logic_mode_start, sizeof(logic_mode_start));
+	/* Initialize the FPGA for logic-analyzer mode. */
+	ret = sigma_fpga_init_la(devc);
+	if (ret != SR_OK)
+		return ret;
 
-	/* Expect a 3 byte reply. */
-	ret = sigma_read(result, 3);
-	if (ret != 3 ||
-	    result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
-		g_warning("Configuration failed. Invalid reply received.");
-		return SIGROK_ERR;
-	}
+	devc->cur_firmware = firmware_idx;
 
-	cur_firmware = firmware_idx;
+	sr_info("Firmware uploaded.");
 
-	return SIGROK_OK;
+	return SR_OK;
 }
 
-static int hw_opendev(int device_index)
+static int dev_open(struct sr_dev_inst *sdi)
 {
-	struct sigrok_device_instance *sdi;
+	struct dev_context *devc;
 	int ret;
 
+	devc = sdi->priv;
+
 	/* Make sure it's an ASIX SIGMA. */
-	if ((ret = ftdi_usb_open_desc(&ftdic,
+	if ((ret = ftdi_usb_open_desc(&devc->ftdic,
 		USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
 
-		g_warning("ftdi_usb_open failed: %s",
-			ftdi_get_error_string(&ftdic));
+		sr_err("ftdi_usb_open failed: %s",
+		       ftdi_get_error_string(&devc->ftdic));
 
 		return 0;
 	}
 
-	if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
-		return SIGROK_ERR;
+	sdi->status = SR_ST_ACTIVE;
 
-	sdi->status = ST_ACTIVE;
-
-	return SIGROK_OK;
+	return SR_OK;
 }
 
-static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
+static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
 {
-	int i, ret;
+	struct dev_context *devc;
+	unsigned int i;
+	int ret;
 
-	sdi = sdi;
+	devc = sdi->priv;
+	ret = SR_OK;
 
-	for (i = 0; supported_samplerates[i]; i++) {
-		if (supported_samplerates[i] == samplerate)
+	for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
+		if (samplerates[i] == samplerate)
 			break;
 	}
-	if (supported_samplerates[i] == 0)
-		return SIGROK_ERR_SAMPLERATE;
+	if (samplerates[i] == 0)
+		return SR_ERR_SAMPLERATE;
 
-	if (samplerate <= MHZ(50)) {
-		ret = upload_firmware(0);
-		num_probes = 16;
+	if (samplerate <= SR_MHZ(50)) {
+		ret = upload_firmware(0, devc);
+		devc->num_channels = 16;
 	}
-	if (samplerate == MHZ(100)) {
-		ret = upload_firmware(1);
-		num_probes = 8;
+	if (samplerate == SR_MHZ(100)) {
+		ret = upload_firmware(1, devc);
+		devc->num_channels = 8;
 	}
-	else if (samplerate == MHZ(200)) {
-		ret = upload_firmware(2);
-		num_probes = 4;
+	else if (samplerate == SR_MHZ(200)) {
+		ret = upload_firmware(2, devc);
+		devc->num_channels = 4;
 	}
 
-	cur_samplerate = samplerate;
-	samples_per_event = 16 / num_probes;
-
-	g_message("Firmware uploaded");
+	devc->cur_samplerate = samplerate;
+	devc->period_ps = 1000000000000ULL / samplerate;
+	devc->samples_per_event = 16 / devc->num_channels;
+	devc->state.state = SIGMA_IDLE;
 
 	return ret;
 }
 
-/* Only trigger on single pin supported (in 100-200 MHz modes). */
-static int configure_probes(GSList *probes)
+/*
+ * In 100 and 200 MHz mode, only a single pin rising/falling can be
+ * set as trigger. In other modes, two rising/falling triggers can be set,
+ * in addition to value/mask trigger for any number of channels.
+ *
+ * The Sigma supports complex triggers using boolean expressions, but this
+ * has not been implemented yet.
+ */
+static int configure_channels(const struct sr_dev_inst *sdi)
 {
-	struct probe *probe;
-	GSList *l;
+	struct dev_context *devc = sdi->priv;
+	const struct sr_channel *ch;
+	const GSList *l;
 	int trigger_set = 0;
+	int channelbit;
 
-	if (cur_samplerate <= MHZ(50)) {
-		g_warning("Trigger support only implemented "
-			  "in 100 and 200 MHz mode.");
-		return SIGROK_ERR;
-	}
+	memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
 
-	for (l = probes; l; l = l->next) {
-		probe = (struct probe *)l->data;
+	for (l = sdi->channels; l; l = l->next) {
+		ch = (struct sr_channel *)l->data;
+		channelbit = 1 << (ch->index);
 
-		if (!probe->enabled || !probe->trigger)
+		if (!ch->enabled || !ch->trigger)
 			continue;
 
-		if (trigger_set) {
-			g_warning("Asix Sigma only supports a single pin trigger "
-				  "in 100 and 200 MHz mode.");
-			return SIGROK_ERR;
-		}
+		if (devc->cur_samplerate >= SR_MHZ(100)) {
+			/* Fast trigger support. */
+			if (trigger_set) {
+				sr_err("Only a single pin trigger in 100 and "
+				       "200MHz mode is supported.");
+				return SR_ERR;
+			}
+			if (ch->trigger[0] == 'f')
+				devc->trigger.fallingmask |= channelbit;
+			else if (ch->trigger[0] == 'r')
+				devc->trigger.risingmask |= channelbit;
+			else {
+				sr_err("Only rising/falling trigger in 100 "
+				       "and 200MHz mode is supported.");
+				return SR_ERR;
+			}
 
-		/* Found trigger. */
-		if (probe->trigger[0] == 'f')
-			triggerfall = 1;
-		else
-			triggerfall = 0;
+			++trigger_set;
+		} else {
+			/* Simple trigger support (event). */
+			if (ch->trigger[0] == '1') {
+				devc->trigger.simplevalue |= channelbit;
+				devc->trigger.simplemask |= channelbit;
+			}
+			else if (ch->trigger[0] == '0') {
+				devc->trigger.simplevalue &= ~channelbit;
+				devc->trigger.simplemask |= channelbit;
+			}
+			else if (ch->trigger[0] == 'f') {
+				devc->trigger.fallingmask |= channelbit;
+				++trigger_set;
+			}
+			else if (ch->trigger[0] == 'r') {
+				devc->trigger.risingmask |= channelbit;
+				++trigger_set;
+			}
+
+			/*
+			 * Actually, Sigma supports 2 rising/falling triggers,
+			 * but they are ORed and the current trigger syntax
+			 * does not permit ORed triggers.
+			 */
+			if (trigger_set > 1) {
+				sr_err("Only 1 rising/falling trigger "
+				       "is supported.");
+				return SR_ERR;
+			}
+		}
 
-		triggerpin = probe->index - 1;
-		trigger_set = 1;
+		if (trigger_set)
+			devc->use_triggers = 1;
 	}
 
-	return SIGROK_OK;
+	return SR_OK;
 }
 
-static void hw_closedev(int device_index)
+static int dev_close(struct sr_dev_inst *sdi)
 {
-	device_index = device_index;
+	struct dev_context *devc;
+
+	devc = sdi->priv;
+
+	/* TODO */
+	if (sdi->status == SR_ST_ACTIVE)
+		ftdi_usb_close(&devc->ftdic);
 
-	ftdi_usb_close(&ftdic);
+	sdi->status = SR_ST_INACTIVE;
+
+	return SR_OK;
 }
 
-static void hw_cleanup(void)
+static int cleanup(void)
 {
+	return dev_clear();
 }
 
-static void *hw_get_device_info(int device_index, int device_info_id)
+static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
+		const struct sr_channel_group *cg)
 {
-	struct sigrok_device_instance *sdi;
-	void *info = NULL;
+	struct dev_context *devc;
 
-	if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
-		fprintf(stderr, "It's NULL.\n");
-		return NULL;
-	}
+	(void)cg;
 
-	switch (device_info_id) {
-	case DI_INSTANCE:
-		info = sdi;
+	switch (id) {
+	case SR_CONF_SAMPLERATE:
+		if (sdi) {
+			devc = sdi->priv;
+			*data = g_variant_new_uint64(devc->cur_samplerate);
+		} else
+			return SR_ERR;
 		break;
-	case DI_NUM_PROBES:
-		info = GINT_TO_POINTER(16);
+	default:
+		return SR_ERR_NA;
+	}
+
+	return SR_OK;
+}
+
+static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
+		const struct sr_channel_group *cg)
+{
+	struct dev_context *devc;
+	uint64_t num_samples;
+	int ret;
+
+	(void)cg;
+
+	if (sdi->status != SR_ST_ACTIVE)
+		return SR_ERR_DEV_CLOSED;
+
+	devc = sdi->priv;
+
+	switch (id) {
+	case SR_CONF_SAMPLERATE:
+		ret = set_samplerate(sdi, g_variant_get_uint64(data));
 		break;
-	case DI_SAMPLERATES:
-		info = &samplerates;
+	case SR_CONF_LIMIT_MSEC:
+		devc->limit_msec = g_variant_get_uint64(data);
+		if (devc->limit_msec > 0)
+			ret = SR_OK;
+		else
+			ret = SR_ERR;
 		break;
-	case DI_TRIGGER_TYPES:
-		info = (char *)TRIGGER_TYPES;
+	case SR_CONF_LIMIT_SAMPLES:
+		num_samples = g_variant_get_uint64(data);
+		devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
 		break;
-	case DI_CUR_SAMPLERATE:
-		info = &cur_samplerate;
+	case SR_CONF_CAPTURE_RATIO:
+		devc->capture_ratio = g_variant_get_uint64(data);
+		if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
+			ret = SR_ERR;
+		else
+			ret = SR_OK;
 		break;
+	default:
+		ret = SR_ERR_NA;
 	}
 
-	return info;
+	return ret;
 }
 
-static int hw_get_status(int device_index)
+static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
+		const struct sr_channel_group *cg)
 {
-	struct sigrok_device_instance *sdi;
+	GVariant *gvar;
+	GVariantBuilder gvb;
 
-	sdi = get_sigrok_device_instance(device_instances, device_index);
-	if (sdi)
-		return sdi->status;
-	else
-		return ST_NOT_FOUND;
-}
+	(void)sdi;
+	(void)cg;
 
-static int *hw_get_capabilities(void)
-{
-	return capabilities;
+	switch (key) {
+	case SR_CONF_DEVICE_OPTIONS:
+		*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
+				hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
+		break;
+	case SR_CONF_SAMPLERATE:
+		g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
+		gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
+				ARRAY_SIZE(samplerates), sizeof(uint64_t));
+		g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
+		*data = g_variant_builder_end(&gvb);
+		break;
+	case SR_CONF_TRIGGER_TYPE:
+		*data = g_variant_new_string(TRIGGER_TYPE);
+		break;
+	default:
+		return SR_ERR_NA;
+	}
+
+	return SR_OK;
 }
 
-static int hw_set_configuration(int device_index, int capability, void *value)
+/* Software trigger to determine exact trigger position. */
+static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
+			      struct sigma_trigger *t)
 {
-	struct sigrok_device_instance *sdi;
-	int ret;
+	int i;
 
-	if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
-		return SIGROK_ERR;
-
-	if (capability == HWCAP_SAMPLERATE) {
-		ret = set_samplerate(sdi, *(uint64_t*) value);
-	} else if (capability == HWCAP_PROBECONFIG) {
-		ret = configure_probes(value);
-	} else if (capability == HWCAP_LIMIT_MSEC) {
-		limit_msec = strtoull(value, NULL, 10);
-		ret = SIGROK_OK;
-	} else if (capability == HWCAP_CAPTURE_RATIO) {
-		capture_ratio = strtoull(value, NULL, 10);
-		ret = SIGROK_OK;
-	} else if (capability == HWCAP_PROBECONFIG) {
-		ret = configure_probes((GSList *) value);
-	} else {
-		ret = SIGROK_ERR;
+	for (i = 0; i < 8; ++i) {
+		if (i > 0)
+			last_sample = samples[i-1];
+
+		/* Simple triggers. */
+		if ((samples[i] & t->simplemask) != t->simplevalue)
+			continue;
+
+		/* Rising edge. */
+		if ((last_sample & t->risingmask) != 0 || (samples[i] &
+		    t->risingmask) != t->risingmask)
+			continue;
+
+		/* Falling edge. */
+		if ((last_sample & t->fallingmask) != t->fallingmask ||
+		    (samples[i] & t->fallingmask) != 0)
+			continue;
+
+		break;
 	}
 
-	return ret;
+	/* If we did not match, return original trigger pos. */
+	return i & 0x7;
+}
+
+
+/*
+ * Return the timestamp of "DRAM cluster".
+ */
+static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
+{
+	return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
 }
 
 /*
@@ -640,31 +947,46 @@ static int hw_set_configuration(int device_index, int capability, void *value)
  * For 50 MHz and below, events contain one sample for each channel,
  * spread 20 ns apart.
  */
-static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
-			   uint16_t *lastsample, int triggerpos, void *user_data)
+static int decode_chunk_ts(struct sigma_dram_line *dram_line, uint16_t *lastts,
+			   uint16_t *lastsample, int triggerpos,
+			   uint16_t events_in_line, void *cb_data)
 {
+	uint8_t *buf = (uint8_t *)dram_line;
+	struct sigma_dram_cluster *dram_cluster;
+	struct sr_dev_inst *sdi = cb_data;
+	struct dev_context *devc = sdi->priv;
 	uint16_t tsdiff, ts;
-	uint16_t samples[65536 * samples_per_event];
-	struct datafeed_packet packet;
+	uint16_t samples[65536 * devc->samples_per_event];
+	struct sr_datafeed_packet packet;
+	struct sr_datafeed_logic logic;
 	int i, j, k, l, numpad, tosend;
 	size_t n = 0, sent = 0;
-	int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
+	int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
 	uint16_t *event;
 	uint16_t cur_sample;
 	int triggerts = -1;
 
-	/* Find in which cluster the trigger occured. */
-	if (triggerpos != -1)
-		triggerts = (triggerpos / 7);
+	/* Check if trigger is in this chunk. */
+	if (triggerpos != -1) {
+		if (devc->cur_samplerate <= SR_MHZ(50))
+			triggerpos -= EVENTS_PER_CLUSTER - 1;
+
+		if (triggerpos < 0)
+			triggerpos = 0;
+
+		/* Find in which cluster the trigger occured. */
+		triggerts = triggerpos / 7;
+	}
 
 	/* For each ts. */
-	for (i = 0; i < 64; ++i) {
-		ts = *(uint16_t *) &buf[i * 16];
+	for (i = 0; i < (events_in_line / 7); i++) {
+		dram_cluster = &dram_line->cluster[i];
+		ts = sigma_dram_cluster_ts(dram_cluster);
 		tsdiff = ts - *lastts;
 		*lastts = ts;
 
 		/* Pad last sample up to current point. */
-		numpad = tsdiff * samples_per_event - clustersize;
+		numpad = tsdiff * devc->samples_per_event - clustersize;
 		if (numpad > 0) {
 			for (j = 0; j < numpad; ++j)
 				samples[j] = *lastsample;
@@ -677,10 +999,12 @@ static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
 		while (sent < n) {
 			tosend = MIN(2048, n - sent);
 
-			packet.type = DF_LOGIC16;
-			packet.length = tosend * sizeof(uint16_t);
-			packet.payload = samples + sent;
-			session_bus(user_data, &packet);
+			packet.type = SR_DF_LOGIC;
+			packet.payload = &logic;
+			logic.length = tosend * sizeof(uint16_t);
+			logic.unitsize = 2;
+			logic.data = samples + sent;
+			sr_session_send(devc->cb_data, &packet);
 
 			sent += tosend;
 		}
@@ -693,172 +1017,416 @@ static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
 		for (j = 0; j < 7; ++j) {
 
 			/* For each sample in event. */
-			for (k = 0; k < samples_per_event; ++k) {
+			for (k = 0; k < devc->samples_per_event; ++k) {
 				cur_sample = 0;
 
-				/* For each probe. */
-				for (l = 0; l < num_probes; ++l)
+				/* For each channel. */
+				for (l = 0; l < devc->num_channels; ++l)
 					cur_sample |= (!!(event[j] & (1 << (l *
-						      samples_per_event + k))))
-						      << l;
+					   devc->samples_per_event + k)))) << l;
 
 				samples[n++] = cur_sample;
 			}
 		}
 
-		*lastsample = samples[n - 1];
-
 		/* Send data up to trigger point (if triggered). */
 		sent = 0;
 		if (i == triggerts) {
 			/*
-			 * Trigger is presumptively only accurate to event, i.e.
-			 * for 100 and 200 MHz, where multiple samples are coded
-			 * in a single event, the trigger does not match the
-			 * exact sample.
+			 * Trigger is not always accurate to sample because of
+			 * pipeline delay. However, it always triggers before
+			 * the actual event. We therefore look at the next
+			 * samples to pinpoint the exact position of the trigger.
 			 */
-			tosend = (triggerpos % 7) - 3;
+			tosend = get_trigger_offset(samples, *lastsample,
+						    &devc->trigger);
 
 			if (tosend > 0) {
-				packet.type = DF_LOGIC16;
-				packet.length = tosend * sizeof(uint16_t);
-				packet.payload = samples;
-				session_bus(user_data, &packet);
+				packet.type = SR_DF_LOGIC;
+				packet.payload = &logic;
+				logic.length = tosend * sizeof(uint16_t);
+				logic.unitsize = 2;
+				logic.data = samples;
+				sr_session_send(devc->cb_data, &packet);
 
 				sent += tosend;
 			}
 
-			packet.type = DF_TRIGGER;
-			packet.length = 0;
-			packet.payload = 0;
-			session_bus(user_data, &packet);
+			/* Only send trigger if explicitly enabled. */
+			if (devc->use_triggers) {
+				packet.type = SR_DF_TRIGGER;
+				sr_session_send(devc->cb_data, &packet);
+			}
 		}
 
 		/* Send rest of the chunk to sigrok. */
 		tosend = n - sent;
 
-		packet.type = DF_LOGIC16;
-		packet.length = tosend * sizeof(uint16_t);
-		packet.payload = samples + sent;
-		session_bus(user_data, &packet);
+		if (tosend > 0) {
+			packet.type = SR_DF_LOGIC;
+			packet.payload = &logic;
+			logic.length = tosend * sizeof(uint16_t);
+			logic.unitsize = 2;
+			logic.data = samples + sent;
+			sr_session_send(devc->cb_data, &packet);
+		}
+
+		*lastsample = samples[n - 1];
 	}
 
-	return SIGROK_OK;
+	return SR_OK;
 }
 
-static int receive_data(int fd, int revents, void *user_data)
+static int download_capture(struct sr_dev_inst *sdi)
 {
-	struct datafeed_packet packet;
+	struct dev_context *devc = sdi->priv;
 	const int chunks_per_read = 32;
-	unsigned char buf[chunks_per_read * CHUNK_SIZE];
-	int bufsz, numchunks, curchunk, i, newchunks;
-	uint32_t triggerpos, stoppos, running_msec;
-	struct timeval tv;
-	uint16_t lastts = 0;
-	uint16_t lastsample = 0;
+	struct sigma_dram_line *dram_line;
+	int bufsz;
+	uint32_t stoppos, triggerpos;
+	struct sr_datafeed_packet packet;
 	uint8_t modestatus;
-	int triggerchunk = -1;
-
-	fd = fd;
-	revents = revents;
-
-	/* Get the current position. */
-	sigma_read_pos(&stoppos, &triggerpos);
-	numchunks = stoppos / 512;
 
-	/* Check if the has expired, or memory is full. */
-	gettimeofday(&tv, 0);
-	running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
-		       (tv.tv_usec - start_tv.tv_usec) / 1000;
+	uint32_t i;
+	uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
+	uint32_t dl_events_in_line = 64 * 7;
+	uint32_t trg_line = ~0;
 
-	if (running_msec < limit_msec && numchunks < 32767)
+	dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
+	if (!dram_line)
 		return FALSE;
 
-	/* Stop acqusition. */
-	sigma_set_register(WRITE_MODE, 0x11);
+	sr_info("Downloading sample data.");
+
+	/* Stop acquisition. */
+	sigma_set_register(WRITE_MODE, 0x11, devc);
 
 	/* Set SDRAM Read Enable. */
-	sigma_set_register(WRITE_MODE, 0x02);
+	sigma_set_register(WRITE_MODE, 0x02, devc);
 
 	/* Get the current position. */
-	sigma_read_pos(&stoppos, &triggerpos);
+	sigma_read_pos(&stoppos, &triggerpos, devc);
 
 	/* Check if trigger has fired. */
-	modestatus = sigma_get_register(READ_MODE);
-	if (modestatus & 0x20) {
-		triggerchunk = triggerpos / 512;
-	}
-
-	/* Download sample data. */
-	for (curchunk = 0; curchunk < numchunks;) {
-		newchunks = MIN(chunks_per_read, numchunks - curchunk);
-
-		g_message("Downloading sample data: %.0f %%",
-			  100.0 * curchunk / numchunks);
-
-		bufsz = sigma_read_dram(curchunk, newchunks, buf);
-
-		/* Find first ts. */
-		if (curchunk == 0)
-			lastts = *(uint16_t *) buf - 1;
-
-		/* Decode chunks and send them to sigrok. */
-		for (i = 0; i < newchunks; ++i) {
-			if (curchunk + i == triggerchunk)
-				decode_chunk_ts(buf + (i * CHUNK_SIZE),
-						&lastts, &lastsample,
-						triggerpos & 0x1ff, user_data);
-			else
-				decode_chunk_ts(buf + (i * CHUNK_SIZE),
-						&lastts, &lastsample,
-						-1, user_data);
+	modestatus = sigma_get_register(READ_MODE, devc);
+	if (modestatus & 0x20)
+		trg_line = triggerpos >> 9;
+
+	/*
+	 * Determine how many 1024b "DRAM lines" do we need to read from the
+	 * Sigma so we have a complete set of samples. Note that the last
+	 * line can be only partial, containing less than 64 clusters.
+	 */
+	dl_lines_total = (stoppos >> 9) + 1;
+
+	dl_lines_done = 0;
+
+	while (dl_lines_total > dl_lines_done) {
+		/* We can download only up-to 32 DRAM lines in one go! */
+		dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
+
+		bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
+					(uint8_t *)dram_line, devc);
+		/* TODO: Check bufsz. For now, just avoid compiler warnings. */
+		(void)bufsz;
+
+		/* This is the first DRAM line, so find the initial timestamp. */
+		if (dl_lines_done == 0) {
+			devc->state.lastts =
+				sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
+			devc->state.lastsample = 0;
 		}
 
-		curchunk += newchunks;
+		for (i = 0; i < dl_lines_curr; i++) {
+			int trigger_line = -1;
+			/* The last "DRAM line" can be only partially full. */
+			if (dl_lines_done + i == dl_lines_total - 1)
+				dl_events_in_line = stoppos & 0x1ff;
+
+			/* Test if the trigger happened on this line. */
+			if (dl_lines_done + i == trg_line)
+				trigger_line = trg_line;
+
+			decode_chunk_ts(dram_line + i,
+					&devc->state.lastts,
+					&devc->state.lastsample,
+					trigger_line,
+					dl_events_in_line, sdi);
+		}
+
+		dl_lines_done += dl_lines_curr;
 	}
 
-	/* End of data. */
-	packet.type = DF_END;
-	packet.length = 0;
-	session_bus(user_data, &packet);
+	/* All done. */
+	packet.type = SR_DF_END;
+	sr_session_send(sdi, &packet);
+
+	dev_acquisition_stop(sdi, sdi);
+
+	g_free(dram_line);
+
+	return TRUE;
+}
+
+/*
+ * Handle the Sigma when in CAPTURE mode. This function checks:
+ * - Sampling time ended
+ * - DRAM capacity overflow
+ * This function triggers download of the samples from Sigma
+ * in case either of the above conditions is true.
+ */
+static int sigma_capture_mode(struct sr_dev_inst *sdi)
+{
+	struct dev_context *devc = sdi->priv;
+
+	uint64_t running_msec;
+	struct timeval tv;
+
+	uint32_t stoppos, triggerpos;
+
+	/* Check if the selected sampling duration passed. */
+	gettimeofday(&tv, 0);
+	running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
+		       (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
+	if (running_msec >= devc->limit_msec)
+		return download_capture(sdi);
+
+	/* Get the position in DRAM to which the FPGA is writing now. */
+	sigma_read_pos(&stoppos, &triggerpos, devc);
+	/* Test if DRAM is full and if so, download the data. */
+	if ((stoppos >> 9) == 32767)
+		return download_capture(sdi);
+
+	return TRUE;
+}
+
+static int receive_data(int fd, int revents, void *cb_data)
+{
+	struct sr_dev_inst *sdi;
+	struct dev_context *devc;
+
+	(void)fd;
+	(void)revents;
+
+	sdi = cb_data;
+	devc = sdi->priv;
+
+	if (devc->state.state == SIGMA_IDLE)
+		return TRUE;
+
+	if (devc->state.state == SIGMA_CAPTURE)
+		return sigma_capture_mode(sdi);
 
 	return TRUE;
 }
 
-static int hw_start_acquisition(int device_index, gpointer session_device_id)
+/* Build a LUT entry used by the trigger functions. */
+static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
+{
+	int i, j, k, bit;
+
+	/* For each quad channel. */
+	for (i = 0; i < 4; ++i) {
+		entry[i] = 0xffff;
+
+		/* For each bit in LUT. */
+		for (j = 0; j < 16; ++j)
+
+			/* For each channel in quad. */
+			for (k = 0; k < 4; ++k) {
+				bit = 1 << (i * 4 + k);
+
+				/* Set bit in entry */
+				if ((mask & bit) &&
+				    ((!(value & bit)) !=
+				    (!(j & (1 << k)))))
+					entry[i] &= ~(1 << j);
+			}
+	}
+}
+
+/* Add a logical function to LUT mask. */
+static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
+				 int index, int neg, uint16_t *mask)
+{
+	int i, j;
+	int x[2][2], tmp, a, b, aset, bset, rset;
+
+	memset(x, 0, 4 * sizeof(int));
+
+	/* Trigger detect condition. */
+	switch (oper) {
+	case OP_LEVEL:
+		x[0][1] = 1;
+		x[1][1] = 1;
+		break;
+	case OP_NOT:
+		x[0][0] = 1;
+		x[1][0] = 1;
+		break;
+	case OP_RISE:
+		x[0][1] = 1;
+		break;
+	case OP_FALL:
+		x[1][0] = 1;
+		break;
+	case OP_RISEFALL:
+		x[0][1] = 1;
+		x[1][0] = 1;
+		break;
+	case OP_NOTRISE:
+		x[1][1] = 1;
+		x[0][0] = 1;
+		x[1][0] = 1;
+		break;
+	case OP_NOTFALL:
+		x[1][1] = 1;
+		x[0][0] = 1;
+		x[0][1] = 1;
+		break;
+	case OP_NOTRISEFALL:
+		x[1][1] = 1;
+		x[0][0] = 1;
+		break;
+	}
+
+	/* Transpose if neg is set. */
+	if (neg) {
+		for (i = 0; i < 2; ++i) {
+			for (j = 0; j < 2; ++j) {
+				tmp = x[i][j];
+				x[i][j] = x[1-i][1-j];
+				x[1-i][1-j] = tmp;
+			}
+		}
+	}
+
+	/* Update mask with function. */
+	for (i = 0; i < 16; ++i) {
+		a = (i >> (2 * index + 0)) & 1;
+		b = (i >> (2 * index + 1)) & 1;
+
+		aset = (*mask >> i) & 1;
+		bset = x[b][a];
+
+		if (func == FUNC_AND || func == FUNC_NAND)
+			rset = aset & bset;
+		else if (func == FUNC_OR || func == FUNC_NOR)
+			rset = aset | bset;
+		else if (func == FUNC_XOR || func == FUNC_NXOR)
+			rset = aset ^ bset;
+
+		if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
+			rset = !rset;
+
+		*mask &= ~(1 << i);
+
+		if (rset)
+			*mask |= 1 << i;
+	}
+}
+
+/*
+ * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
+ * simple pin change and state triggers. Only two transitions (rise/fall) can be
+ * set at any time, but a full mask and value can be set (0/1).
+ */
+static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
+{
+	int i,j;
+	uint16_t masks[2] = { 0, 0 };
+
+	memset(lut, 0, sizeof(struct triggerlut));
+
+	/* Contant for simple triggers. */
+	lut->m4 = 0xa000;
+
+	/* Value/mask trigger support. */
+	build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
+			lut->m2d);
+
+	/* Rise/fall trigger support. */
+	for (i = 0, j = 0; i < 16; ++i) {
+		if (devc->trigger.risingmask & (1 << i) ||
+		    devc->trigger.fallingmask & (1 << i))
+			masks[j++] = 1 << i;
+	}
+
+	build_lut_entry(masks[0], masks[0], lut->m0d);
+	build_lut_entry(masks[1], masks[1], lut->m1d);
+
+	/* Add glue logic */
+	if (masks[0] || masks[1]) {
+		/* Transition trigger. */
+		if (masks[0] & devc->trigger.risingmask)
+			add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
+		if (masks[0] & devc->trigger.fallingmask)
+			add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
+		if (masks[1] & devc->trigger.risingmask)
+			add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
+		if (masks[1] & devc->trigger.fallingmask)
+			add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
+	} else {
+		/* Only value/mask trigger. */
+		lut->m3 = 0xffff;
+	}
+
+	/* Triggertype: event. */
+	lut->params.selres = 3;
+
+	return SR_OK;
+}
+
+static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
 {
-	struct sigrok_device_instance *sdi;
-	struct datafeed_packet packet;
-	struct datafeed_header header;
+	struct dev_context *devc;
 	struct clockselect_50 clockselect;
-	int frac;
-	uint8_t triggerselect;
+	int frac, triggerpin, ret;
+	uint8_t triggerselect = 0;
 	struct triggerinout triggerinout_conf;
+	struct triggerlut lut;
 
-	session_device_id = session_device_id;
+	if (sdi->status != SR_ST_ACTIVE)
+		return SR_ERR_DEV_CLOSED;
 
-	if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
-		return SIGROK_ERR;
+	devc = sdi->priv;
 
-	device_index = device_index;
+	if (configure_channels(sdi) != SR_OK) {
+		sr_err("Failed to configure channels.");
+		return SR_ERR;
+	}
 
-	/* If the samplerate has not been set, default to 50 MHz. */
-	if (cur_firmware == -1)
-		set_samplerate(sdi, MHZ(50));
+	/* If the samplerate has not been set, default to 200 kHz. */
+	if (devc->cur_firmware == -1) {
+		if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
+			return ret;
+	}
 
 	/* Enter trigger programming mode. */
-	sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
+	sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
 
 	/* 100 and 200 MHz mode. */
-	if (cur_samplerate >= MHZ(100)) {
-		sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81);
+	if (devc->cur_samplerate >= SR_MHZ(100)) {
+		sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
+
+		/* Find which pin to trigger on from mask. */
+		for (triggerpin = 0; triggerpin < 8; ++triggerpin)
+			if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
+			    (1 << triggerpin))
+				break;
 
-		triggerselect = (1 << LEDSEL1) | (triggerfall << 3) |
-					(triggerpin & 0x7);
+		/* Set trigger pin and light LED on trigger. */
+		triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
+
+		/* Default rising edge. */
+		if (devc->trigger.fallingmask)
+			triggerselect |= 1 << 3;
 
 	/* All other modes. */
-	} else if (cur_samplerate <= MHZ(50)) {
-		sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
+	} else if (devc->cur_samplerate <= SR_MHZ(50)) {
+		build_basic_trigger(&lut, devc);
+
+		sigma_write_trigger_lut(&lut, devc);
 
 		triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
 	}
@@ -870,81 +1438,84 @@ static int hw_start_acquisition(int device_index, gpointer session_device_id)
 
 	sigma_write_register(WRITE_TRIGGER_OPTION,
 			     (uint8_t *) &triggerinout_conf,
-			     sizeof(struct triggerinout));
+			     sizeof(struct triggerinout), devc);
 
 	/* Go back to normal mode. */
-	sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect);
+	sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
 
 	/* Set clock select register. */
-	if (cur_samplerate == MHZ(200))
-		/* Enable 4 probes. */
-		sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
-	else if (cur_samplerate == MHZ(100))
-		/* Enable 8 probes. */
-		sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
+	if (devc->cur_samplerate == SR_MHZ(200))
+		/* Enable 4 channels. */
+		sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
+	else if (devc->cur_samplerate == SR_MHZ(100))
+		/* Enable 8 channels. */
+		sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
 	else {
 		/*
 		 * 50 MHz mode (or fraction thereof). Any fraction down to
 		 * 50 MHz / 256 can be used, but is not supported by sigrok API.
 		 */
-		frac = MHZ(50) / cur_samplerate - 1;
+		frac = SR_MHZ(50) / devc->cur_samplerate - 1;
 
 		clockselect.async = 0;
 		clockselect.fraction = frac;
-		clockselect.disabled_probes = 0;
+		clockselect.disabled_channels = 0;
 
 		sigma_write_register(WRITE_CLOCK_SELECT,
 				     (uint8_t *) &clockselect,
-				     sizeof(clockselect));
+				     sizeof(clockselect), devc);
 	}
 
 	/* Setup maximum post trigger time. */
-	sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 256) / 100);
+	sigma_set_register(WRITE_POST_TRIGGER,
+			   (devc->capture_ratio * 255) / 100, devc);
 
 	/* Start acqusition. */
-	gettimeofday(&start_tv, 0);
-	sigma_set_register(WRITE_MODE, 0x0d);
+	gettimeofday(&devc->start_tv, 0);
+	sigma_set_register(WRITE_MODE, 0x0d, devc);
+
+	devc->cb_data = cb_data;
 
 	/* Send header packet to the session bus. */
-	packet.type = DF_HEADER;
-	packet.length = sizeof(struct datafeed_header);
-	packet.payload = &header;
-	header.feed_version = 1;
-	gettimeofday(&header.starttime, NULL);
-	header.samplerate = cur_samplerate;
-	header.protocol_id = PROTO_RAW;
-	header.num_probes = num_probes;
-	session_bus(session_device_id, &packet);
+	std_session_send_df_header(cb_data, LOG_PREFIX);
 
 	/* Add capture source. */
-	source_add(0, G_IO_IN, 10, receive_data, session_device_id);
+	sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
+
+	devc->state.state = SIGMA_CAPTURE;
 
-	return SIGROK_OK;
+	return SR_OK;
 }
 
-static void hw_stop_acquisition(int device_index, gpointer session_device_id)
+static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
 {
-	device_index = device_index;
-	session_device_id = session_device_id;
+	struct dev_context *devc;
 
-	/* Stop acquisition. */
-	sigma_set_register(WRITE_MODE, 0x11);
-
-	// XXX Set some state to indicate that data should be sent to sigrok
-	//     Now, we just wait for timeout
-}
-
-struct device_plugin asix_sigma_plugin_info = {
-	"asix-sigma",
-	1,
-	hw_init,
-	hw_cleanup,
-	hw_opendev,
-	hw_closedev,
-	hw_get_device_info,
-	hw_get_status,
-	hw_get_capabilities,
-	hw_set_configuration,
-	hw_start_acquisition,
-	hw_stop_acquisition,
+	(void)cb_data;
+
+	devc = sdi->priv;
+	devc->state.state = SIGMA_IDLE;
+
+	sr_source_remove(0);
+
+	return SR_OK;
+}
+
+SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
+	.name = "asix-sigma",
+	.longname = "ASIX SIGMA/SIGMA2",
+	.api_version = 1,
+	.init = init,
+	.cleanup = cleanup,
+	.scan = scan,
+	.dev_list = dev_list,
+	.dev_clear = dev_clear,
+	.config_get = config_get,
+	.config_set = config_set,
+	.config_list = config_list,
+	.dev_open = dev_open,
+	.dev_close = dev_close,
+	.dev_acquisition_start = dev_acquisition_start,
+	.dev_acquisition_stop = dev_acquisition_stop,
+	.priv = NULL,
 };