X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=fx2lafw.c;h=f69955161eb18b88aeda21a5775e7c4658e34a78;hb=c430e296be053c17d4d5f40c53378d401ab07a17;hp=bc97e5a711ea5e5be01b6c90fd2bd89d7299dae2;hpb=dc7ac8bfeea9cae7bbfee5839889a3b37f3d62f5;p=sigrok-firmware-fx2lafw.git

diff --git a/fx2lafw.c b/fx2lafw.c
index bc97e5a7..f6995516 100644
--- a/fx2lafw.c
+++ b/fx2lafw.c
@@ -46,6 +46,13 @@
 #include <eputils.h>
 #include <gpif.h>
 
+/* Protocol commands */
+#define CMD_SET_SAMPLERATE	0xb0
+#define CMD_START		0xb1
+#define CMD_STOP		0xb2
+#define CMD_GET_FW_VERSION	0xb3
+/* ... */
+
 #define SYNCDELAY() SYNCDELAY4
 
 /* ... */
@@ -243,15 +250,6 @@ static void gpif_init_la(void)
 
 static void setup_endpoints(void)
 {
-	/* Setup EP1 (OUT). */
-	EP1OUTCFG = (1 << 7) |		  /* EP is valid/activated */
-		    (0 << 6) |		  /* Reserved */
-		    (1 << 5) | (0 << 4) | /* EP Type: bulk */
-		    (0 << 3) |		  /* Reserved */
-		    (0 << 2) |		  /* Reserved */
-		    (0 << 1) | (0 << 0);  /* Reserved */
-	SYNCDELAY();
-
 	/* Setup EP2 (IN). */
 	EP2CFG = (1 << 7) |		  /* EP is valid/activated */
 		 (1 << 6) |		  /* EP direction: IN */
@@ -261,18 +259,36 @@ static void setup_endpoints(void)
 		 (0 << 1) | (0 << 0);	  /* EP buffering: quad buffering */
 	SYNCDELAY();
 
-	/* Disable all other EPs (EP4, EP6, and EP8). */
-	EP4CFG &= ~bmVALID;
-	SYNCDELAY();
+	/* Setup EP6 (IN) in the debug build. */
+#ifdef DEBUG
+	EP6CFG = (1 << 7) |		  /* EP is valid/activated */
+		 (1 << 6) |		  /* EP direction: IN */
+		 (1 << 5) | (0 << 4) |	  /* EP Type: bulk */
+		 (0 << 3) |		  /* EP buffer size: 512 */
+		 (0 << 2) |		  /* Reserved */
+		 (1 << 1) | (0 << 0);	  /* EP buffering: double buffering */
+#else
 	EP6CFG &= ~bmVALID;
+#endif
+	SYNCDELAY();
+
+	/* Disable all other EPs (EP4 and EP8). */
+	EP1INCFG &= ~bmVALID;
+	SYNCDELAY();
+	EP1OUTCFG &= ~bmVALID;
+	SYNCDELAY();
+	EP4CFG &= ~bmVALID;
 	SYNCDELAY();
 	EP8CFG &= ~bmVALID;
 	SYNCDELAY();
 
-	/* Reset the FIFOs of EP1 and EP2. */
+	/* EP2: Reset the FIFOs. */
 	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
-	RESETFIFO(0x01)
 	RESETFIFO(0x02)
+#ifdef DEBUG
+	/* Reset the FIFOs of EP6 when in debug mode. */
+	RESETFIFO(0x06)
+#endif
 
 	/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
 	EP2FIFOCFG = bmAUTOIN | ~bmWORDWIDE;
@@ -284,14 +300,35 @@ static void setup_endpoints(void)
 	EP2AUTOINLENL = 0x00;
 	SYNCDELAY();
 
-	/* Set the GPIF flag for EP2 to 'full'. */
+	/* EP2: Set the GPIF flag to 'full'. */
 	EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
 	SYNCDELAY();
 }
 
 BOOL handle_vendorcommand(BYTE cmd)
 {
-	(void)cmd;
+	/* Protocol implementation */
+
+	switch (cmd) {
+	case CMD_SET_SAMPLERATE:
+		/* TODO */
+		break;
+	case CMD_START:
+		/* TODO */
+		break;
+	case CMD_STOP:
+		GPIFABORT = 0xff;
+		/* TODO */
+		return TRUE;
+		break;
+	case CMD_GET_FW_VERSION:
+		/* TODO */
+		break;
+	default:
+		/* Unimplemented command. */
+		break;
+	}
+
 	return FALSE;
 }
 
@@ -317,16 +354,16 @@ BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
 
 	/* (2) Reset data toggles of the EPs in the interface. */
 	/* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
-	RESETTOGGLE(0x01);
 	RESETTOGGLE(0x82);
+	RESETTOGGLE(0x76);
 
 	/* (3) Restore EPs to their default conditions. */
 	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
-	RESETFIFO(0x01);
-	/* TODO */
 	RESETFIFO(0x02);
 	/* TODO */
 
+	RESETFIFO(0x06);
+
 	/* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
 
 	return TRUE;
@@ -370,7 +407,7 @@ void hispeed_isr(void) interrupt HISPEED_ISR
 void main(void)
 {
 	/* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
-	REVCTL = (1 << 1) | (1 << 0);
+	REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;
 
 	got_sud = FALSE;