X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;h=cdbebebf27e2c2f0ceb8e02beab7afc5f00d538b;hb=cd4a074dcfa09713de7a0ae6259d9a18eab3582f;hp=bcfcdbdab9dc779998d7d85e9cd73f0c10494b85;hpb=4c180223a8ae12feb7bc3601e07e848fb9cdb493;p=libsigrokdecode.git

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index bcfcdbd..cdbebeb 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -71,8 +71,8 @@ class Decoder(srd.Decoder):
     desc     = 'Zilog Z80 microprocessor disassembly.'
     license  = 'gplv3+'
     inputs   = ['logic']
-    outputs  = ['z80']
-    tags = ['Logic', 'MCU Debugging']
+    outputs  = []
+    tags     = ['Retro computing']
     channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
@@ -93,15 +93,15 @@ class Decoder(srd.Decoder):
         } for i in range(16)
     )
     annotations = (
-        ('addr',  'Memory or I/O address'),
+        ('addr', 'Memory or I/O address'),
         ('memrd', 'Byte read from memory'),
         ('memwr', 'Byte written to memory'),
-        ('iord',  'Byte read from I/O port'),
-        ('iowr',  'Byte written to I/O port'),
+        ('iord', 'Byte read from I/O port'),
+        ('iowr', 'Byte written to I/O port'),
         ('instr', 'Z80 CPU instruction'),
-        ('rop',   'Value of input operand'),
-        ('wop',   'Value of output operand'),
-        ('warn',  'Warning message'),
+        ('rop', 'Value of input operand'),
+        ('wop', 'Value of output operand'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('addrbus', 'Address bus', (Ann.ADDR,)),