X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;fp=decoders%2Fz80%2Fpd.py;h=4663f955124e2e5b2f51457dcca8d75d1275815e;hb=3831aa891c7a9822a376023419a1fea1a698463c;hp=8fadff59afa1680a1c17d36e9bfe82c98ff897ec;hpb=739f9313539c559949748d918e59865496ad8f6e;p=libsigrokdecode.git

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index 8fadff5..4663f95 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -291,9 +291,9 @@ class Decoder(srd.Decoder):
         if self.want_imm > 0:
             return OpState.IMM1
         self.ann_dasm = Ann.INSTR
-        if self.want_read > 0:
+        if self.want_read > 0 and self.prev_cycle in (Cycle.MEMRD, Cycle.IORD):
             return OpState.ROP1
-        if self.want_write > 0:
+        if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR):
             return OpState.WOP1
         return OpState.RESTART
 
@@ -302,18 +302,18 @@ class Decoder(srd.Decoder):
         if self.want_imm > 1:
             return OpState.IMM2
         self.ann_dasm = Ann.INSTR
-        if self.want_read > 0:
+        if self.want_read > 0 and self.prev_cycle in (Cycle.MEMRD, Cycle.IORD):
             return OpState.ROP1
-        if self.want_write > 0:
+        if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR):
             return OpState.WOP1
         return OpState.RESTART
 
     def on_state_IMM2(self):
         self.arg_imm |= self.pend_data << 8
         self.ann_dasm = Ann.INSTR
-        if self.want_read > 0:
+        if self.want_read > 0 and self.prev_cycle in (Cycle.MEMRD, Cycle.IORD):
             return OpState.ROP1
-        if self.want_write > 0:
+        if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR):
             return OpState.WOP1
         return OpState.RESTART
 
@@ -334,7 +334,7 @@ class Decoder(srd.Decoder):
         self.arg_read |= self.pend_data << 8
         self.mnemonic = '{ro:04X}'
         self.ann_dasm = Ann.ROP
-        if self.want_write > 0:
+        if self.want_write > 0 and self.prev_cycle in (Cycle.MEMWR, Cycle.IOWR):
             return OpState.WOP1
         return OpState.RESTART