X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fx2444m%2Fpd.py;h=8a2852adecf33d0f9428f294b372c576ed731935;hb=d6d8a8a440ea2a81e6ddde33d16bc84d01cdb432;hp=e061d624522e1ee9e7ea92990bee6eb9a87a20f1;hpb=c40477def76ec5e8ddccc36cff5769a451d569e7;p=libsigrokdecode.git

diff --git a/decoders/x2444m/pd.py b/decoders/x2444m/pd.py
index e061d62..8a2852a 100644
--- a/decoders/x2444m/pd.py
+++ b/decoders/x2444m/pd.py
@@ -21,18 +21,16 @@ import re
 import sigrokdecode as srd
 
 registers = {
-    0x80: ['WRDS',  lambda _: ''],
-    0x81: ['STO',   lambda _: ''],
-    0x82: ['SLEEP', lambda _: ''],
-    0x83: ['WRITE', lambda v: '0x%x' % v],
-    0x84: ['WREN',  lambda _: ''],
-    0x85: ['RCL',   lambda _: ''],
-    0x86: ['READ',  lambda v: '0x%x' % v],
-    0x87: ['READ',  lambda v: '0x%x' % v],
+    0x80: ['WRDS',  0, lambda _: ''],
+    0x81: ['STO',   1, lambda _: ''],
+    0x82: ['SLEEP', 2, lambda _: ''],
+    0x83: ['WRITE', 3, lambda v: '0x%x' % v],
+    0x84: ['WREN',  4, lambda _: ''],
+    0x85: ['RCL',   5, lambda _: ''],
+    0x86: ['READ',  6, lambda v: '0x%x' % v],
+    0x87: ['READ',  7, lambda v: '0x%x' % v],
 }
 
-ann_write, ann_read = range(2)
-
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'x2444m'
@@ -42,32 +40,36 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['spi']
     outputs = ['x2444m']
+    tags = ['IC', 'Memory']
     annotations = (
-        ('write', 'Commands and data written to the device'),
-        ('read', 'Data read from the device'),
-    )
-    annotation_rows = (
-        ('data', 'Data', (ann_write, ann_read)),
+        ('wrds', 'Write disable'),
+        ('sto', 'Store RAM data in EEPROM'),
+        ('sleep', 'Enter sleep mode'),
+        ('write', 'Write data into RAM'),
+        ('wren', 'Write enable'),
+        ('rcl', 'Recall EEPROM data into RAM'),
+        ('read', 'Data read from RAM'),
+        ('read', 'Data read from RAM'),
     )
 
     def __init__(self):
         self.reset()
 
     def reset(self):
-        pass
-
-    def start(self):
-        self.out_ann = self.register(srd.OUTPUT_ANN)
         self.cs_start = 0
         self.cs_asserted = False
         self.cmd_digit = 0
 
-    def putreadwrite(self, ss, es, reg, addr, value):
+    def start(self):
+        self.out_ann = self.register(srd.OUTPUT_ANN)
+
+    def putreadwrite(self, ss, es, reg, idx, addr, value):
         self.put(ss, es, self.out_ann,
-                 [ann_write, ['%s: %s => 0x%4.4x' % (reg, addr, value)]])
+                 [idx, ['%s: %s => 0x%4.4x' % (reg, addr, value),
+                        '%s: %s => 0x%4.4x' % (reg[0], addr, value), reg[0]]])
 
-    def putcmd(self, ss, es, reg):
-        self.put(ss, es, self.out_ann, [ann_write, ['%s' % reg]])
+    def putcmd(self, ss, es, reg, idx):
+        self.put(ss, es, self.out_ann, [idx, [reg, reg[0]]])
 
     def decode(self, ss, es, data):
         ptype, mosi, miso = data
@@ -89,17 +91,17 @@ class Decoder(srd.Decoder):
             if not self.cs_asserted:
                 # Only one digit, simple command. Else read/write.
                 if self.cmd_digit == 1:
-                    name, decoder = registers[self.addr & 0x87]
-                    self.putcmd(self.addr_start, es, name)
+                    name, idx, decoder = registers[self.addr & 0x87]
+                    self.putcmd(self.addr_start, es, name, idx)
                 elif self.cmd_digit > 1:
-                    name, decoder = registers[self.addr & 0x87]
+                    name, idx, decoder = registers[self.addr & 0x87]
                     if name == 'READ':
                         value = self.read_value
                     elif name == 'WRITE':
                         value = self.write_value
                     else:
                         value = 0
-                    self.putreadwrite(self.addr_start, es, name,
+                    self.putreadwrite(self.addr_start, es, name, idx,
                                       decoder((self.addr >> 3) & 0x0f), value)
 
             if self.cs_asserted: