X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=f039aa329426d3df02840eb53c4c94010d1816fe;hb=6fbab493aaee26f9ecba0268261d1f3264339d9d;hp=f514c480e32079f0f3e648d92ae06dfb497a48a4;hpb=b413721ccb254e99cf8b8991bb1adf2fb26b53a6;p=libsigrokdecode.git diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index f514c48..f039aa3 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -33,12 +33,13 @@ Packet: - 'BIT', - 'STUFF BIT', None - 'EOP', None + - 'ERR', None : - 'J', 'K', 'SE0', or 'SE1' : - - 0 or 1 + - '0' or '1' - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'. ''' @@ -66,8 +67,18 @@ bitrates = { 'full-speed': 12000000, # 12Mb/s (+/- 0.25%) } +sym_annotation = { + 'J': [0, ['J']], + 'K': [1, ['K']], + 'SE0': [2, ['SE0', '0']], + 'SE1': [3, ['SE1', '1']], +} + +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'usb_signalling' name = 'USB signalling' longname = 'Universal Serial Bus (LS/FS) signalling' @@ -75,7 +86,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['usb_signalling'] - probes = ( + channels = ( {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, ) @@ -84,29 +95,34 @@ class Decoder(srd.Decoder): 'default': 'full-speed', 'values': ('full-speed', 'low-speed')}, ) annotations = ( - ('sym', 'Symbol'), + ('sym-j', 'J symbol'), + ('sym-k', 'K symbol'), + ('sym-se0', 'SE0 symbol'), + ('sym-se1', 'SE1 symbol'), ('sop', 'Start of packet (SOP)'), ('eop', 'End of packet (EOP)'), ('bit', 'Bit'), ('stuffbit', 'Stuff bit'), + ('error', 'Error'), ) annotation_rows = ( - ('bits', 'Bits', (1, 2, 3, 4)), - ('symbols', 'Symbols', (0,)), + ('bits', 'Bits', (4, 5, 6, 7, 8)), + ('symbols', 'Symbols', (0, 1, 2, 3)), ) def __init__(self): self.samplerate = None self.oldsym = 'J' # The "idle" state is J. - self.ss_sop = None self.ss_block = None self.samplenum = 0 - self.syms = [] self.bitrate = None self.bitwidth = None - self.bitnum = 0 + self.samplepos = None self.samplenum_target = None + self.samplenum_edge = None + self.samplenum_lastedge = 0 self.oldpins = None + self.edgepins = None self.consecutive_ones = 0 self.state = 'IDLE' @@ -119,58 +135,64 @@ class Decoder(srd.Decoder): self.samplerate = value self.bitrate = bitrates[self.options['signalling']] self.bitwidth = float(self.samplerate) / float(self.bitrate) - self.halfbit = int(self.bitwidth / 2) def putpx(self, data): - self.put(self.samplenum, self.samplenum, self.out_python, data) + s = self.samplenum_edge + self.put(s, s, self.out_python, data) def putx(self, data): - self.put(self.samplenum, self.samplenum, self.out_ann, data) + s = self.samplenum_edge + self.put(s, s, self.out_ann, data) def putpm(self, data): - s, h = self.samplenum, self.halfbit - self.put(self.ss_block - h, s + h, self.out_python, data) + e = self.samplenum_edge + self.put(self.ss_block, e, self.out_python, data) def putm(self, data): - s, h = self.samplenum, self.halfbit - self.put(self.ss_block - h, s + h, self.out_ann, data) + e = self.samplenum_edge + self.put(self.ss_block, e, self.out_ann, data) def putpb(self, data): - s, h = self.samplenum, self.halfbit - self.put(s - h, s + h, self.out_python, data) + s, e = self.samplenum_lastedge, self.samplenum_edge + self.put(s, e, self.out_python, data) def putb(self, data): - s, h = self.samplenum, self.halfbit - self.put(s - h, s + h, self.out_ann, data) + s, e = self.samplenum_lastedge, self.samplenum_edge + self.put(s, e, self.out_ann, data) def set_new_target_samplenum(self): - bitpos = self.ss_sop + (self.bitwidth / 2) - bitpos += self.bitnum * self.bitwidth - self.samplenum_target = int(bitpos) + self.samplepos += self.bitwidth; + self.samplenum_target = int(self.samplepos) + self.samplenum_lastedge = self.samplenum_edge + self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2)) def wait_for_sop(self, sym): # Wait for a Start of Packet (SOP), i.e. a J->K symbol change. if sym != 'K': self.oldsym = sym return - self.ss_sop = self.samplenum + self.consecutive_ones = 0 + self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5 self.set_new_target_samplenum() self.putpx(['SOP', None]) - self.putx([1, ['SOP', 'S']]) + self.putx([4, ['SOP', 'S']]) self.state = 'GET BIT' - def handle_bit(self, sym, b): - if self.consecutive_ones == 6 and b == '0': - # Stuff bit. - self.putpb(['STUFF BIT', None]) - self.putb([4, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]]) - self.putb([0, ['%s' % sym]]) - self.consecutive_ones = 0 + def handle_bit(self, b): + if self.consecutive_ones == 6: + if b == '0': + # Stuff bit. + self.putpb(['STUFF BIT', None]) + self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']]) + self.consecutive_ones = 0 + else: + self.putpb(['ERR', None]) + self.putb([8, ['Bit stuff error', 'BS ERR', 'B']]) + self.state = 'IDLE' else: # Normal bit (not a stuff bit). self.putpb(['BIT', b]) - self.putb([3, ['%s' % b]]) - self.putb([0, ['%s' % sym]]) + self.putb([6, ['%s' % b]]) if b == '1': self.consecutive_ones += 1 else: @@ -178,37 +200,48 @@ class Decoder(srd.Decoder): def get_eop(self, sym): # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J. - self.syms.append(sym) - self.putpb(['SYM', sym]) - self.putb([0, ['%s' % sym, '%s' % sym[0]]]) - self.bitnum += 1 self.set_new_target_samplenum() + self.putpb(['SYM', sym]) + self.putb(sym_annotation[sym]) self.oldsym = sym - if self.syms[-2:] == ['SE0', 'J']: + if sym == 'SE0': + pass + elif sym == 'J': # Got an EOP. self.putpm(['EOP', None]) - self.putm([2, ['EOP', 'E']]) - self.bitnum, self.syms, self.state = 0, [], 'IDLE' - self.consecutive_ones = 0 + self.putm([5, ['EOP', 'E']]) + self.state = 'IDLE' + self.bitwidth = float(self.samplerate) / float(self.bitrate) + else: + self.putpm(['ERR', None]) + self.putm([8, ['EOP Error', 'EErr', 'E']]) + self.state = 'IDLE' def get_bit(self, sym): + self.set_new_target_samplenum() if sym == 'SE0': - # Start of an EOP. Change state, run get_eop() for this bit. + # Start of an EOP. Change state, save edge self.state = 'GET EOP' - self.ss_block = self.samplenum - self.get_eop(sym) - return - self.syms.append(sym) + self.ss_block = self.samplenum_lastedge + else: + b = '0' if self.oldsym != sym else '1' + self.handle_bit(b) self.putpb(['SYM', sym]) - b = '0' if self.oldsym != sym else '1' - self.handle_bit(sym, b) - self.bitnum += 1 - self.set_new_target_samplenum() + self.putb(sym_annotation[sym]) + if self.oldsym != sym: + edgesym = symbols[self.options['signalling']][tuple(self.edgepins)] + if edgesym not in ('SE0', 'SE1'): + if edgesym == sym: + self.bitwidth = self.bitwidth - (0.001 * self.bitwidth) + self.samplepos = self.samplepos - (0.01 * self.bitwidth) + else: + self.bitwidth = self.bitwidth + (0.001 * self.bitwidth) + self.samplepos = self.samplepos + (0.01 * self.bitwidth) self.oldsym = sym def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') for (self.samplenum, pins) in data: # State machine. if self.state == 'IDLE': @@ -218,8 +251,11 @@ class Decoder(srd.Decoder): self.oldpins = pins sym = symbols[self.options['signalling']][tuple(pins)] self.wait_for_sop(sym) + self.edgepins = pins elif self.state in ('GET BIT', 'GET EOP'): # Wait until we're in the middle of the desired bit. + if self.samplenum == self.samplenum_edge: + self.edgepins = pins if self.samplenum < self.samplenum_target: continue sym = symbols[self.options['signalling']][tuple(pins)] @@ -227,6 +263,3 @@ class Decoder(srd.Decoder): self.get_bit(sym) elif self.state == 'GET EOP': self.get_eop(sym) - else: - raise Exception('Invalid state: %s' % self.state) -