X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=c60075c548b0ea840b7ed6e34c25cfeaecc7fb23;hb=502acfc2c71a2bbc97d4d7597150cd479bead1ee;hp=4dfde832236351309aff3cb844430a3e2e4e506a;hpb=831d893d4b9e4f76b5e645ee5e6fcfd4962ffa6a;p=libsigrokdecode.git

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 4dfde83..c60075c 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -69,10 +69,23 @@ symbols = {
         (0, 1): 'LS_J',
         (1, 1): 'SE1',
     },
+    # After a PREamble PID, the bus segment between Host and Hub uses LS
+    # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
+    # both upstream and downstream low-speed data, the hub is responsible for
+    # inverting the polarity of the data before transmitting to/from a
+    # low-speed port.").
+    'low-speed-rp': {
+        # (<dp>, <dm>): <symbol/state>
+        (0, 0): 'SE0',
+        (1, 0): 'J',
+        (0, 1): 'K',
+        (1, 1): 'SE1',
+    },
 }
 
 bitrates = {
-    'low-speed': 1500000,   # 1.5Mb/s (+/- 1.5%)
+    'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+    'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
     'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
     'automatic': None
 }
@@ -136,6 +149,7 @@ class Decoder(srd.Decoder):
         self.oldpins = None
         self.edgepins = None
         self.consecutive_ones = 0
+        self.bits = None
         self.state = 'INIT'
 
     def start(self):
@@ -188,6 +202,7 @@ class Decoder(srd.Decoder):
         if sym != 'K' or self.oldsym != 'J':
             return
         self.consecutive_ones = 0
+        self.bits = ''
         self.update_bitrate()
         self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
         self.set_new_target_samplenum()
@@ -227,7 +242,7 @@ class Decoder(srd.Decoder):
             # Got an EOP.
             self.putpm(['EOP', None])
             self.putm([5, ['EOP', 'E']])
-            self.state = 'IDLE'
+            self.state = 'WAIT IDLE'
         else:
             self.putpm(['ERR', None])
             self.putm([8, ['EOP Error', 'EErr', 'E']])
@@ -235,16 +250,26 @@ class Decoder(srd.Decoder):
 
     def get_bit(self, sym):
         self.set_new_target_samplenum()
+        b = '0' if self.oldsym != sym else '1'
+        self.oldsym = sym
         if sym == 'SE0':
             # Start of an EOP. Change state, save edge
             self.state = 'GET EOP'
             self.ss_block = self.samplenum_lastedge
         else:
-            b = '0' if self.oldsym != sym else '1'
             self.handle_bit(b)
         self.putpb(['SYM', sym])
         self.putb(sym_annotation[sym])
-        if self.oldsym != sym:
+        if len(self.bits) <= 16:
+            self.bits += b
+        if len(self.bits) == 16 and self.bits == '0000000100111100':
+            # Sync and low-speed PREamble seen
+            self.putpx(['EOP', None])
+            self.state = 'IDLE'
+            self.signalling = 'low-speed-rp'
+            self.update_bitrate()
+            self.oldsym = 'J'
+        if b == '0':
             edgesym = symbols[self.signalling][tuple(self.edgepins)]
             if edgesym not in ('SE0', 'SE1'):
                 if edgesym == sym:
@@ -253,7 +278,6 @@ class Decoder(srd.Decoder):
                 else:
                     self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
                     self.samplepos = self.samplepos + (0.01 * self.bitwidth)
-        self.oldsym = sym
 
     def handle_idle(self, sym):
         self.samplenum_edge = self.samplenum