X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb%2F__init__.py;h=77b58d11a509806fe6d280cb4fcaff70c512bad1;hb=156509ca42f0df2380c9f205f9aad337e1a07802;hp=068cadff5c5291111824c19e238baaeca6b749ae;hpb=94bbdb9a4146ec5eaa56411706dc92de3a92f2d8;p=libsigrokdecode.git

diff --git a/decoders/usb/__init__.py b/decoders/usb/__init__.py
index 068cadf..77b58d1 100644
--- a/decoders/usb/__init__.py
+++ b/decoders/usb/__init__.py
@@ -18,5 +18,27 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+'''
+USB (full-speed) protocol decoder.
+
+Full-speed USB signalling consists of two signal lines, both driven at 3.3V
+logic levels. The signals are DP (D+) and DM (D-), and normally operate in
+differential mode.
+The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
+A state SE0 is defined where DP=DM=0. This common mode signal is used to
+signal a reset or end of packet.
+
+Data transmitted on the USB is encoded with NRZI. A transition from J to K
+or vice-versa indicates a logic 0, while no transition indicates a logic 1.
+If 6 ones are transmitted consecutively, a zero is inserted to force a
+transition. This is known as bit stuffing. Data is transferred at a rate
+of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit
+intervals long.
+
+Details:
+https://en.wikipedia.org/wiki/USB
+http://www.usb.org/developers/docs/
+'''
+
 from .usb import *