X-Git-Url: http://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fuart.py;h=bb4d9e62c22e75f9b1513e9c8ab42a9b4e799b11;hb=a465436e627578f69c403de75a89522dfd883217;hp=6c9fdee8087e967e041e4e7b8de4e9335b05baa9;hpb=122e9a90a54e034b93f554938896983d293edec1;p=libsigrokdecode.git

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 6c9fdee..bb4d9e6 100644
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -61,7 +61,7 @@ class Decoder(srd.Decoder):
     id = 'uart'
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
-    desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
+    desc = 'Asynchronous, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
@@ -265,10 +265,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either RX or TX could be omitted (optional probe).
-        for (samplenum, (rx, tx)) in data:
-
-            # TODO: Start counting at 0 or 1? Increase before or after?
-            self.samplenum += 1
+        for (self.samplenum, (rx, tx)) in data:
 
             # First sample: Save RX/TX value.
             if self.oldbit[RX] == None: